DSPIC33FJ256GP710-I/PF Microchip Technology Inc., DSPIC33FJ256GP710-I/PF Datasheet - Page 194

• Manufacturer Part Number: DSPIC33FJ256GP710-I/PF
• Description: 16 BIT MCU/DSP 100LD 40MIPS 256KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ256GP710-I/PF

• A/d Inputs: 32-Channels, 12-Bit
• Comparators: 8
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 85
• Interface: CAN/I2C/SPI/UART
• Ios: 85
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 100-pin TQFP
• Programmable Memory: 256K Bytes
• Ram Size: 30K Bytes
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6
• Lead Free Status / Rohs Status: RoHS Compliant part

dsPIC33F
REGISTER 15-10: FLTBCON: FAULT B CONTROL REGISTER
DS70165D-page 192
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
Note 1:
FBOV4H
FLTBM
R/W-0
R/W-0
Fault A pin has priority over Fault B pin, if enabled.
FBOVxH<4:1>:FBOVxL<4:1>: Fault Input B PWM Override Value bits
1 = The PWM output pin is driven active on an external Fault input event
0 = The PWM output pin is driven inactive on an external Fault input event
FLTBM: Fault B Mode bit
1 = The Fault B input pin functions in the Cycle-by-Cycle mode
0 = The Fault B input pin latches all control pins to the programmed states in FLTBCON<15:8>
Unimplemented: Read as ‘0’
FBEN4: Fault Input B Enable bit
1 = PWM4H/PWM4L pin pair is controlled by Fault Input B
0 = PWM4H/PWM4L pin pair is not controlled by Fault Input B
FBEN3: Fault Input B Enable bit
1 = PWM3H/PWM3L pin pair is controlled by Fault Input B
0 = PWM3H/PWM3L pin pair is not controlled by Fault Input B
FBEN2: Fault Input B Enable bit
1 = PWM2H/PWM2L pin pair is controlled by Fault Input B
0 = PWM2H/PWM2L pin pair is not controlled by Fault Input B
FBEN1: Fault Input B Enable bit
1 = PWM1H/PWM1L pin pair is controlled by Fault Input B
0 = PWM1H/PWM1L pin pair is not controlled by Fault Input B
FBOV4L
R/W-0
U-0
—
W = Writable bit
‘1’ = Bit is set
FBOV3H
R/W-0
U-0
—
FBOV3L
R/W-0
(1)
(1)
(1)
(1)
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
FBEN4
FBOV2H
R/W-0
R/W-0
(1)
FBEN3
FBOV2L
R/W-0
R/W-0
(1)
© 2006 Microchip Technology Inc.
x = Bit is unknown
FBEN2
FBOV1H
R/W-0
R/W-0
(1)
FBEN1
FBOV1L
R/W-0
R/W-0
bit 8
bit 0
(1)