DSPIC30F3014-30I/P Microchip Technology Inc., DSPIC30F3014-30I/P Datasheet - Page 83

• Manufacturer Part Number: DSPIC30F3014-30I/P
• Description: DSP, 16-Bit, 24 KB Flash, 2KB RAM, 30 I/O, PDIP-40
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F3014-30I/P

• A/d Inputs: 13-Channels, 12-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 30
• Interface: CAN, I2C, SPI, UART/USART
• Ios: 30
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 40-pin PDIP
• Programmable Memory: 24K Bytes
• Ram Size: 2K Bytes
• Timers: 3-16-bit, 1-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

13.0
This section describes the output compare module and
associated operational modes. The features provided
by this module are useful in applications requiring
operational modes, such as:
• Generation of Variable Width Output Pulses
• Power Factor Correction
Figure 13-1 depicts a block diagram of the output
compare module.
The key operational features of the output compare
module include:
• Timer2 and Timer3 Selection mode
• Simple Output Compare Match mode
• Dual Output Compare Match mode
FIGURE 13-1:
© 2007 Microchip Technology Inc.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
Note:
OUTPUT COMPARE MODULE
From GP
Timer Module
TMR2<15:0
Where ‘x’ is shown, reference is made to the registers associated with the respective output compare
channels 1 through N.
0
OUTPUT COMPARE MODE BLOCK DIAGRAM
Comparator
OCxRS
OCxR
TMR3<15:0>
1
OCTSEL
T2P2_MATCH
0
• Simple PWM mode
• Output Compare During Sleep and Idle modes
• Interrupt on Output Compare/PWM Event
These operating modes are determined by setting the
appropriate bits in the 16-bit OCxCON SFR (where
x = 1,2,3,...,N). The dsPIC DSC devices contain up to
8 compare channels (i.e., the maximum value of N is 8).
The dsPIC30F3014 device contains 2 compare
channels while the dsPIC30F4013 device contains 4
compare channels.
OCxRS and OCxR in Figure 13-1 represent the Dual
Compare registers. In the Dual Compare mode, the
OCxR register is used for the first compare and OCxRS
is used for the second compare.
13.1
Each output compare channel can select between one
of two 16-bit timers, Timer2 or Timer3.
The selection of the timers is controlled by the OCTSEL
bit (OCxCON<3>). Timer2 is the default timer resource
for the output compare module.
T3P3_MATCH
Mode Select
OCM<2:0>
dsPIC30F3014/4013
1
Output
3
Logic
Timer2 and Timer3 Selection Mode
Set Flag bit
OCxIF
S
R
Q
Output
Enable
(for x = 1, 2, 3 or 4)
(for x = 5, 6, 7 or 8)
or OCFB
OCFA
DS70138E-page 81
OCx