PIC32MX795F512H-80I/PT Microchip Technology Inc., PIC32MX795F512H-80I/PT Datasheet - Page 68
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PIC32MX795F512H-80I/PT
Manufacturer Part Number
PIC32MX795F512H-80I/PT
Description
512KB Flash, 128KB RAM, 80 MHz, USB, ENET, 2xCAN, 8 DMA
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC32MX795F512H-80IPT.pdf
(254 pages)
Specifications of PIC32MX795F512H-80I/PT
A/d Inputs
16-Channel, 10-Bit
Comparators
2
Eeprom Memory
0 Bytes
Input Output
53
Interface
CAN/I2C/SPI/UART/USB
Memory Type
Flash
Number Of Bits
32
Package Type
64-pin TQFP
Programmable Memory
512K Bytes
Ram Size
128K Bytes
Speed
80 MHz
Temperature Range
–40 to +85 °C
Timers
5-16-bit
Voltage, Range
2.3-3.6 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX795F512H-80I/PT
Manufacturer:
MICROCHIP
Quantity:
218
Company:
Part Number:
PIC32MX795F512H-80I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC32MX795F512H-80I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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TABLE 4-6:
Legend:
Note
10D0
10E0
10F0
1100
1110
1120
1130
1140
1150
1:
2:
IPC10
IPC12
IPC11
IPC4
IPC5
IPC6
IPC7
IPC8
IPC9
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
These bits are not available on PIC32MX664 devices.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
INTERRUPT REGISTER MAP FOR PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND
PIC32MX695F512L DEVICES
31/15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30/14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
29/13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
28/12
—
DMA7IP<2:0>
DMA5IP<2:0>
(1)
CMP1IP<2:0>
RTCCIP<2:0>
DMA3IP<2:0>
DMA1IP<2:0>
INT4IP<2:0>
SPI1IP<2:0>
SPI2IP<2:0>
AD1IP<2:0>
I2C1IP<2:0>
I2C4IP<2:0>
I2C2IP<2:0>
USBIP<2:0>
IC4IP<2:0>
IC5IP<2:0>
U3IP<2:0>
U5IP<2:0>
U4IP<2:0>
(CONTINUED)
27/11
—
(2)
(2)
26/10
—
25/9
DMA7IS<1:0>
DMA5IS<1:0>
—
CMP1IS<1:0>
RTCCIS<1:0>
DMA3IS<1:0>
DMA1IS<1:0>
INT4IS<1:0>
SPI1IS<1:0>
SPI2IS<1:0>
AD1IS<1:0>
I2C1IS<1:0>
I2C4IS<1:0>
I2C2IS<1:0>
USBIS<1:0>
IC4IS<1:0>
IC5IS<1:0>
U3IS<1:0>
U5IS<1:0>
U4IS<1:0>
24/8
—
(2)
(2)
Bits
23/7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
22/6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
21/5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
20/4
—
Section 12.1.1 “CLR, SET and INV Registers”
DMA6IP<2:0>
DMA4IP<2:0>
FSCMIP<2:0>
CMP2IP<2:0>
DMA2IP<2:0>
DMA0IP<2:0>
SPI3IP<2:0>
I2C3IP<2:0>
PMPIP<2:0>
SPI4IP<2:0>
I2C5IP<2:0>
OC4IP<2:0>
OC5IP<2:0>
FCEIP<2:0>
ETHIP<2:0>
CNIP<2:0>
T4IP<2:0>
T5IP<2:0>
U1IP<2:0>
U2IP<2:0>
U6IP<2:0>
19/3
—
(2)
(2)
18/2
—
17/1
DMA6IS<1:0>
DMA4IS<1:0>
—
CMP2IS<1:0>
FSCMIS<1:0>
DMA2IS<1:0>
DMA0IS<1:0>
SPI3IS<1:0>
I2C3IS<1:0>
PMPIS<1:0>
SPI4IS<1:0>
I2C5IS<1:0>
OC4IS<1:0>
OC5IS<1:0>
FCEIS<1:0>
ETHIS<1:0>
CNIS<1:0>
T4IS<1:0>
T5IS<1:0>
U1IS<1:0>
U2IS<1:0>
U6IS<1:0>
16/0
—
for more
(2)
(2)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
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