PIC32MX795F512H-80I/PT Microchip Technology Inc., PIC32MX795F512H-80I/PT Datasheet - Page 85
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC32MX795F512H-80I/PT
Manufacturer Part Number
PIC32MX795F512H-80I/PT
Description
512KB Flash, 128KB RAM, 80 MHz, USB, ENET, 2xCAN, 8 DMA
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC32MX795F512H-80IPT.pdf
(254 pages)
Specifications of PIC32MX795F512H-80I/PT
A/d Inputs
16-Channel, 10-Bit
Comparators
2
Eeprom Memory
0 Bytes
Input Output
53
Interface
CAN/I2C/SPI/UART/USB
Memory Type
Flash
Number Of Bits
32
Package Type
64-pin TQFP
Programmable Memory
512K Bytes
Ram Size
128K Bytes
Speed
80 MHz
Temperature Range
–40 to +85 °C
Timers
5-16-bit
Voltage, Range
2.3-3.6 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX795F512H-80I/PT
Manufacturer:
MICROCHIP
Quantity:
218
Company:
Part Number:
PIC32MX795F512H-80I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC32MX795F512H-80I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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TABLE 4-19:
Legend:
Note
3180 DCH1DSIZ
3190 DCH1SPTR
31A0 DCH1DPTR
31B0 DCH1CSIZ
31C0 DCH1CPTR
31D0 DCH1DAT
31E0 DCH2CON
31F0 DCH2ECON
3200
3210 DCH2SSA
3220 DCH2DSA
3230 DCH2SSIZ
3240 DCH2DSIZ
3250 DCH2SPTR
3260 DCH2DPTR
3270 DCH2CSIZ
3280 DCH2CPTR
1:
DCH2INT
2:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
DMA channels 4-7 are note available on PIC32MX534/564/664/764 devices.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
DMA CHANNELS 0-7 REGISTER MAP
CHBUSY
31/15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30/14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
29/13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
28/12
—
—
—
—
—
—
—
—
—
—
CHSIRQ<7:0>
—
—
—
—
—
—
—
—
27/11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1,2)
26/10
(CONTINUED)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
25/9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHCHNS
24/8
CHSPTR<15:0>
CHDPTR<15:0>
CHCPTR<15:0>
CHSPTR<15:0>
CHDPTR<15:0>
CHCPTR<15:0>
CHDSIZ<15:0>
CHCSIZ<15:0>
CHSSIZ<15:0>
CHDSIZ<15:0>
CHCSIZ<15:0>
CHSSA<31:0>
CHDSA<31:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bits
CFORCE
CHSDIE
CHSDIF
CHEN
23/7
—
—
—
—
—
—
—
—
—
—
—
—
—
CABORT
CHSHIE
CHAED
CHSHIF
22/6
—
—
—
—
—
—
—
—
—
—
—
—
—
CHDDIE
CHDDIF
CHCHN
PATEN
21/5
—
—
—
—
—
—
—
—
—
—
—
—
—
SIRQEN
CHDHIE
CHDHIF
CHAEN
20/4
Section 12.1.1 “CLR, SET and INV Registers”
CHPDAT<7:0>
—
—
—
—
—
—
—
CHAIRQ<7:0>
—
—
—
—
—
—
AIRQEN
CHBCIE
CHBCIF
19/3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHEDET
CHCCIE
CHCCIF
18/2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHTAIE
CHTAIF
17/1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHPRI<1:0>
CHERIE 0000
CHERIF
for more
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
00FF
FF00
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
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