PIC18F4620-I/P Microchip Technology Inc., PIC18F4620-I/P Datasheet - Page 292
PIC18F4620-I/P
Manufacturer Part Number
PIC18F4620-I/P
Description
40 Pin, 64 KB Flash, 3968 RAM, 36 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F4620-IP.pdf
(390 pages)
Specifications of PIC18F4620-I/P
A/d Inputs
13-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
1024 Bytes
Input Output
36
Interface
SPI/I2C/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
64K Bytes
Ram Size
4K Bytes
Speed
40 MHz
Timers
1-8 bit, 3-16 bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Manufacturer
Quantity
Price
Part Number:
PIC18F4620-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
PIC18F4620-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F4620-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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PIC18F2525/2620/4525/4620
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39626B-page 290
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
W
Q1
=
=
Inclusive OR Literal with W
IORLW k
0
(W) .OR. k
N, Z
The contents of W are ORed with the
eight-bit literal ‘k’. The result is placed in
W.
1
1
IORLW
literal ‘k’
Read
0000
Q2
k
9Ah
BFh
255
1001
35h
W
Process
Data
Q3
kkkk
Write to W
Q4
kkkk
Preliminary
IORWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
RESULT =
W
RESULT =
W
Q1
=
=
register ‘f’
Inclusive OR W with f
IORWF
0
d
a
(W) .OR. (f)
N, Z
Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is placed back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
IORWF
Read
0001
Q2
13h
91h
13h
93h
f
[0,1]
[0,1]
2004 Microchip Technology Inc.
255
RESULT, 0, 1
f {,d {,a}}
00da
Process
dest
Data
Q3
95 (5Fh). See
ffff
destination
Write to
Q4
ffff
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