PIC18F4620-I/P Microchip Technology Inc., PIC18F4620-I/P Datasheet - Page 385

• Manufacturer Part Number: PIC18F4620-I/P
• Description: 40 Pin, 64 KB Flash, 3968 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4620-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 36
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 64K Bytes
• Ram Size: 4K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Timer3 .............................................................................. 135
Timing Diagrams
 2004 Microchip Technology Inc.
16-Bit Read/Write Mode ........................................... 137
Associated Registers ............................................... 137
Operation ................................................................. 136
Oscillator .......................................................... 135, 137
Overflow Interrupt ............................................ 135, 137
Special Event Trigger (CCP) .................................... 137
TMR3H Register ...................................................... 135
TMR3L Register ....................................................... 135
A/D Conversion ........................................................ 360
Acknowledge Sequence .......................................... 194
Asynchronous Reception ......................................... 214
Asynchronous Transmission .................................... 212
Asynchronous Transmission
Automatic Baud Rate Calculation ............................ 210
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 215
Baud Rate Generator with Clock Arbitration ............ 188
BRG Overflow Sequence ......................................... 210
BRG Reset Due to SDA Arbitration
Brown-out Reset (BOR) ........................................... 346
Bus Collision During a Repeated Start
Bus Collision During a Repeated Start
Bus Collision During a
Bus Collision During a
Bus Collision During a
Bus Collision During Start
Bus Collision for Transmit and
Capture/Compare/PWM (CCP) ................................ 348
CLKO and I/O .......................................................... 345
Clock Synchronization ............................................. 181
Clock/Instruction Cycle .............................................. 57
Example SPI Master Mode (CKE = 0) ..................... 350
Example SPI Master Mode (CKE = 1) ..................... 351
Example SPI Slave Mode (CKE = 0) ....................... 352
Example SPI Slave Mode (CKE = 1) ....................... 353
External Clock (All Modes except PLL) .................... 343
Fail-Safe Clock Monitor ............................................ 262
First Start Bit Timing ................................................ 189
Full-Bridge PWM Output .......................................... 153
Half-Bridge PWM Output ......................................... 152
High/Low-Voltage Detect Characteristics ................ 340
High-Voltage Detect Operation
I
I
I
I
I
I
I
I
I
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 354
C Bus Start/Stop Bits ............................................. 354
C Master Mode (7 or
C Master Mode (7-Bit Reception) .......................... 193
C Slave Mode (10-Bit Reception, SEN = 0) .......... 178
C Slave Mode (10-Bit Reception, SEN = 1) .......... 183
C Slave Mode (10-Bit Transmission) ..................... 179
C Slave Mode (7-Bit Reception, SEN = 0) ............ 176
C Slave Mode (7-Bit Reception, SEN = 1) ............ 182
(Back to Back) ................................................. 212
Normal Operation ............................................ 215
During Start Condition ..................................... 197
Condition (Case 1) ........................................... 198
Condition (Case 2) ........................................... 198
Start Condition (SCL = 0) ................................. 197
Stop Condition (Case 1) .................................. 199
Stop Condition (Case 2) .................................. 199
Condition (SDA Only) ...................................... 196
Acknowledge ................................................... 195
(VDIRMAG = 1) ................................................ 246
10-Bit Transmission) ........................................ 192
PIC18F2525/2620/4525/4620
Preliminary
I
I
I
Low-Voltage Detect Operation
Master SSP I
Master SSP I
Parallel Slave Port
Parallel Slave Port (PSP) Read ............................... 121
Parallel Slave Port (PSP) Write ............................... 121
PWM Auto-Shutdown (PRSEN = 0,
PWM Auto-Shutdown (PRSEN = 1,
PWM Direction Change ........................................... 155
PWM Direction Change at Near
PWM Output ............................................................ 144
Repeat Start Condition ............................................ 190
Reset, Watchdog Timer (WDT),
Send Break Character Sequence ............................ 216
Slave Synchronization ............................................. 167
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ........................................ 166
SPI Mode (Slave Mode, CKE = 0) ........................... 168
SPI Mode (Slave Mode, CKE = 1) ........................... 168
Synchronous Reception (Master Mode,
Synchronous Transmission ..................................... 217
Synchronous Transmission
Time-out Sequence on POR w/PLL
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 347
Transition for Entry to Idle Mode ............................... 38
Transition for Entry to SEC_RUN Mode .................... 35
Transition for Entry to Sleep Mode ............................ 37
Transition for Two-Speed Start-up
Transition for Wake from Idle to
Transition for Wake from Sleep (HSPLL) .................. 37
Transition from RC_RUN Mode to
Transition from SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 36
USART Synchronous Receive
USART Synchronous Transmission
2
2
2
C Slave Mode (7-Bit Transmission) ...................... 177
C Slave Mode General Call Address
C Stop Condition Receive or
Sequence (7 or 10-Bit Address Mode) ............ 184
Transmit Mode ................................................. 194
(VDIRMAG = 0) ............................................... 245
(PIC18F4410/4510/4515/4610) ....................... 349
Auto-Restart Disabled) .................................... 158
Auto-Restart Enabled) ..................................... 158
100% Duty Cycle ............................................. 155
Oscillator Start-up Timer (OST),
Power-up Timer (PWRT) ................................. 346
V
SREN) ............................................................. 219
(Through TXEN) .............................................. 218
Enabled (MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
(INTOSC to HSPLL) ........................................ 260
Run Mode .......................................................... 38
PRI_RUN Mode ................................................. 36
PRI_RUN Mode (HSPLL) .................................. 35
(Master/Slave) ................................................. 358
(Master/Slave) ................................................. 358
DD
Rise > T
2
2
C Bus Data ....................................... 356
C Bus Start/Stop Bits ........................ 356
PWRT
DD
) ............................................ 47
, V
DD
DD
DD
, Case 1) ...................... 46
, Case 2) ...................... 46
Rise < T
DD
DD
) ............................ 47
DS39626B-page 383
,
PWRT
) ........... 46