PIC18F252-I/SP Microchip Technology Inc., PIC18F252-I/SP Datasheet - Page 81

• Manufacturer Part Number: PIC18F252-I/SP
• Description: Microcontroller; 32 KB Flash; 1536 RAM; 256 EEPROM; 25 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F252-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

REGISTER 8-5:
© 2006 Microchip Technology Inc.
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
bit 7
Unimplemented: Read as '0'
EEIF: Data EEPROM/FLASH Write Operation Interrupt Flag bit
1 = The Write operation is complete (must be cleared in software)
0 = The Write operation is not complete, or has not been started
BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision occurred (must be cleared in software)
0 = No bus collision occurred
LVDIF: Low Voltage Detect Interrupt Flag bit
1 = A low voltage condition occurred (must be cleared in software)
0 = The device voltage is above the Low Voltage Detect trip point
TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed (must be cleared in software)
0 = TMR3 register did not overflow
CCP2IF: CCPx Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
Legend:
R = Readable bit
- n = Value at POR
U-0
—
U-0
—
W = Writable bit
’1’ = Bit is set
U-0
—
R/W-0
EEIF
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
R/W-0
BCLIF
R/W-0
LVDIF
PIC18FXX2
TMR3IF
x = Bit is unknown
R/W-0
DS39564C-page 79
CCP2IF
R/W-0
bit 0