PIC18F8520-I/PT Microchip Technology Inc., PIC18F8520-I/PT Datasheet - Page 340

• Manufacturer Part Number: PIC18F8520-I/PT
• Description: 80 PIN, 32 KB FLASH, 2048 RAM, 68 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8520-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 68
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F6520/8520/6620/8620/6720/8720
TABLE 26-22: MASTER SSP I
DS39609B-page 338
100
101
102
103
90
91
106
107
92
109
110
D102
Note 1:
Param
No.
2:
T
T
T
T
T
T
T
T
T
T
T
C
Symbol
SU
SU
SU
AA
HIGH
LOW
R
F
HD
HD
BUF
B
Maximum pin capacitance = 10 pF for all I
A fast mode I
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the
SCL line is released.
:
:
:
:
:
STA
DAT
STO
STA
DAT
Clock High Time 100 kHz mode
Clock Low Time 100 kHz mode
SDA and SCL
Rise Time
SDA and SCL
Fall Time
Start Condition
Setup Time
Start Condition
Hold Time
Data Input
Hold Time
Data Input
Setup Time
Stop Condition
Setup Time
Output Valid
from Clock
Bus Free Time
Bus Capacitive Loading
2
C bus device can be used in a standard mode I
Characteristic
2
C BUS DATA REQUIREMENTS
400 kHz mode
1 MHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
2
C pins.
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
OSC
OSC
OSC
OSC
OSC
OSC
20 + 0.1 C
20 + 0.1 C
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
TBD
TBD
TBD
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
Min
250
100
4.7
1.3
—
—
—
—
—
—
—
—
0
0
B
B
2
C bus system, but parameter #107
1000
3500
1000
Max
300
300
300
300
100
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
 2004 Microchip Technology Inc.
C
10 to 400 pF
C
10 to 400 pF
Only relevant for
Repeated Start condition
After this period, the first
clock pulse is generated
(Note 2)
Time the bus must be free
before a new transmission
can start
B
B
is specified to be from
is specified to be from
Conditions
250 ns,