DSPIC33FJ64MC506-I/PT Microchip Technology Inc., DSPIC33FJ64MC506-I/PT Datasheet - Page 359
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DSPIC33FJ64MC506-I/PT
Manufacturer Part Number
DSPIC33FJ64MC506-I/PT
Description
DSP, 16-Bit, 64KB Flash, 8KB RAM, 53 I/O, TQFP-64
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC33FJ64MC506-IPT.pdf
(370 pages)
Specifications of DSPIC33FJ64MC506-I/PT
A/d Inputs
16-Channels, 12-Bit
Comparators
8
Cpu Speed
40 MIPS
Eeprom Memory
0 Bytes
Input Output
53
Interface
CAN, I2C, SPI, UART/USART
Ios
53
Memory Type
Flash
Number Of Bits
16
Package Type
64-pin TQFP
Programmable Memory
64K Bytes
Ram Size
8K Bytes
Timers
9-16-bit, 4-32-bit
Voltage, Range
3-3.6
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Price
Company:
Part Number:
DSPIC33FJ64MC506-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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APPENDIX A:
Revision A (October 2005)
• Initial release of this document
Revision B (February 2006)
• Updated Register descriptions and memory maps
• Revised Oscillator section
• Updated ADC characteristics
• Updated Thermal Packaging characteristics
Revision C (March 2006)
• Information related to prototype samples removed
• Flash memory characteristics updated
• Incorrect references to SPI FIFO buffers
• DC Characteristics updated
• Device Configuration registers updated
Revision D (July 2006)
• Added FBS and FSS Device Configuration regis-
• Added INTTREG Interrupt Control and Status reg-
• Added Core Registers BSRAM and SSRAM (see
• Clarified Fail-Safe Clock Monitor operation (see
• Updated COSC<2:0> and NOSC<2:0> bit config-
• Updated CLKDIV register bit configurations (see
• Added Word Write Cycle Time parameter (T
• Noted exceptions to Absolute Maximum Ratings
• Added ADC2 Event Trigger for Timer4/5
• Corrected mislabeled 2COV bit in I2CxSTAT reg-
• Added QEI Register descriptions (see
• Corrected mislabeled PMOD<4:1> field in PWM-
• Corrected mislabeled UPDN_SRC bit in QEICON
© 2007 Microchip Technology Inc.
removed. These buffers are not supported by the
dsPIC33F family.
ters (see Table 23-1) and corresponding bit field
descriptions (see Table 23-2). These added regis-
ters replaced the former RESERVED1 and
RESERVED2 registers.
ister. (See Section 6.3 “Interrupt Control and
Status Registers”. See also Register 6-33.)
Section 3.2.8 “Data Ram Protection Feature”)
Section 8.3 “Fail-Safe Clock Monitor (FSCM)”)
urations in OSCCON register (see Register 8-1)
Register 8-2)
to Program Flash Memory (see Table 26-11)
on I/O pin output current (see Section 26.0
“Electrical Characteristics”)
(Section 12.0 “Timer2/3, Timer4/5, Timer6/7
and Timer8/9”)
ister (see Table 18-1)
Register 16-1 and Register 16-2)
CON register (see Register 15-5)
register (see Register 16-1)
REVISION HISTORY
WW
)
Preliminary
• Corrected mislabeled I2COV bit in I2CxCON
• Removed AD26a, AD27a, AD28a, AD26b,
Revision E (January 2007)
• This revision includes updates to the packaging
register (see Register 18-1)
AD27b, AD28b from Table 26-40 (ADC Module).
diagrams.
dsPIC33F
DS70165E-page 357
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