DSPIC33FJ64MC506-I/PT Microchip Technology Inc., DSPIC33FJ64MC506-I/PT Datasheet - Page 94
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DSPIC33FJ64MC506-I/PT
Manufacturer Part Number
DSPIC33FJ64MC506-I/PT
Description
DSP, 16-Bit, 64KB Flash, 8KB RAM, 53 I/O, TQFP-64
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC33FJ64MC506-IPT.pdf
(370 pages)
Specifications of DSPIC33FJ64MC506-I/PT
A/d Inputs
16-Channels, 12-Bit
Comparators
8
Cpu Speed
40 MIPS
Eeprom Memory
0 Bytes
Input Output
53
Interface
CAN, I2C, SPI, UART/USART
Ios
53
Memory Type
Flash
Number Of Bits
16
Package Type
64-pin TQFP
Programmable Memory
64K Bytes
Ram Size
8K Bytes
Timers
9-16-bit, 4-32-bit
Voltage, Range
3-3.6
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ64MC506-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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dsPIC33F
REGISTER 6-1:
REGISTER 6-2:
DS70165E-page 92
bit 15
bit 7
Legend:
C = Clear only bit
S = Set only bit
‘1’ = Bit is set
bit 7-5
Note 1:
bit 15
bit 7
Legend:
R = Readable bit
0’ = Bit is cleared
bit 3
Note 1:
R/W-0
IPL2
R/W-0
SATA
R-0
U-0
OA
—
2:
3:
2:
(2)
(3)
For complete register details, see Register 2-1: “SR: CPU STATUS Register”.
The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
For complete register details, see Register 2-2: “CORCON: CORE Control Register”.
The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
IPL<2:0>: CPU Interrupt Priority Level Status bits
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
IPL3: CPU Interrupt Priority Level Status bit 3
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
R/W-0
IPL1
R/W-0
SATB
R-0
U-0
OB
—
SR: CPU STATUS REGISTER
CORCON: CORE CONTROL REGISTER
(2)
(3)
‘0’ = Bit is cleared
W = Writable bit
R = Readable bit
W = Writable bit
C = Clear only bit
‘x = Bit is unknown
R/W-0
SATDW
IPL0
R/W-1
R/C-0
U-0
SA
—
(2)
(3)
ACCSAT
R/W-0
R/W-0
R/C-0
R-0
SB
RA
US
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
-n = Value at POR
x = Bit is unknown
-n = Value at POR
U = Unimplemented bit, read as ‘0’
(2)
IPL3
R/W-0
R/W-0
R/C-0
OAB
EDT
R-0
N
(1)
(2)
(1)
R/W-0
R/W-0
R/C-0
SAB
PSV
R-0
OV
© 2007 Microchip Technology Inc.
‘1’ = Bit is set
DL<2:0>
R/W-0
R/W-0
RND
R -0
R-0
DA
Z
R/W-0
R/W-0
R/W-0
R-0
DC
IF
C
bit 8
bit 0
bit 8
bit 0
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