DS3251+ Maxim Integrated Products, DS3251+ Datasheet - Page 16

• Manufacturer Part Number: DS3251+
• Description: IC LIU DS3/E3/STS-1 144-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS3251+

• Number Of Drivers/receivers: 1/1
• Protocol: DS3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit
Name
Default
Status Register Description
The status registers have two types of status bits. Real-time status bits—located in the
state of a signal at the time it was read. Latched status bits—located in the
changes state (low-to-high, high-to-low, or both, depending on the bit) and cleared when written with a logic 1
value. After clearing, latched status bits remain cleared until the signal changes state again. Interrupt-enable bits—
located in the
Figure 7-1. Status Register Logic
Bit 7: E3 Mode Enable (E3M)
Bit 6: STS-1 Mode Enable (STS)
Bits 5, 4: Local Loopback, Remote Loopback Select (LLB, RLB)
Bits 3, 2: Transmitter Data Select (TDSA, TDSB). See
Bit 0: Reset (RST). When this bit is high, the digital logic of the LIU is held in reset and all registers for that LIU
(except the RST bit) are forced to their default values. RST is cleared to 0 at power-up and when the RST pin is
activated.
0 = DS3 operation
1 = E3 or STS-1 operation
When E3M = 1,
0 = E3 operation
1 = STS-1 operation
When E3M = 0, STS selects the DS3 AIS pattern
00 = no loopback
01 = remote loopback
10 = analog local loopback
11 = digital local loopback
0 = normal operation
1 = reset LIU
EVENT
SRIE
WR
WR
E3M
7
0
registers—control whether or not the INT pin is driven low when latched register bits are set.
LATCHED STATUS REGISTER
STS
INT ENABLE
CLEAR ON WRITE LOGIC 1
6
0
REGISTER
SET ON EVENT DETECT
GCRn
Global Configuration Register
00h, 10h, 20h, 30h
LLB
5
0
16 of 71
RLB
Table 6-G
4
0
(Table
OTHER INT
SOURCE
REAL-TIME STATUS
6-G).
TDSA
for details.
3
0
LATCHED STATUS
SRL
TDSB
registers—are set when a signal
0
2
SR
registers—indicate the
—
—
1
SR
SRL
INT
RST
0
0