DS3251+ Maxim Integrated Products, DS3251+ Datasheet - Page 26

• Manufacturer Part Number: DS3251+
• Description: IC LIU DS3/E3/STS-1 144-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS3251+

• Number Of Drivers/receivers: 1/1
• Protocol: DS3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In E3 mode, HDB3 decoding is performed. RLCV is asserted during any RCLK cycle where the data on RDAT
causes one of the following code violations:
When RLCV is asserted to flag a BPV, the RDAT pin outputs a one. The state bit that tracks the polarity of the last
BPV is toggled on every BPV, whether part of a valid B3ZS/HDB3 codeword or not.
To support a glueless interface to a variety of neighboring components, the polarity of RCLK can be inverted.
Normally, data is output on the RPOS/RDAT and RNEG/RLCV pins on the falling edge of RCLK. To output data on
these pins on the rising edge of RCLK, pull the RCINV pin high (hardware mode) or set the RCINV configuration bit
in the
The RCLK, RPOS/RDAT, and RNEG/RLCV pins can be tri-stated to support protection switching and redundant-
LIU applications. This tri-stating capability supports system configurations where two or more LIUs are wire-ORed
together and a system processor selects one to be active. To tri-state RCLK, RPOS/RDAT, and RNEG/RLCV,
assert the RTS pin or the RTS configuration bit in the
8.7 Receive Line-Code Violation Counter
The line-code violation counter is always enabled regardless of the settings of the RBIN pin or the RBIN
configuration bit. The receiver has an internal 16-bit saturating counter and a 16-bit latch, which the CPU can read
as registers
cleared when the receive code-violation counter update bit, RCR:RCVUD, is changed from a zero to a one. The
RCVUD bit must be cleared back to a zero before a new update can occur. If there is an LCV increment pulse and
an update pulse in the same clock period, the counter is preset to a one rather than cleared so that the LCV is not
missed. The counter is incremented when the RLCV pin flags a code violation as described in Section 8.6. The
counter saturates at 65,535 (0FFFFh) and does not roll over.
8.8 Receiver Power-Down
To minimize power consumption when the receiver is not being used, assert the RPD configuration bit in the
register (CPU bus mode). When the receiver is powered down, the RCLK, RPOS/RDAT, and RNEG/RLCV pins are
tri-stated. In addition, the RXP and RXN pins become high impedance.
8.9 Receiver Jitter Tolerance
The receiver exceeds the input jitter tolerance requirements of all applicable telecommunication standards in
1-A. See
Hardware mode or ITU bit set to 0
–
–
–
ITU bit set to 1
–
RCR
A BPV immediately preceded by a valid pulse (B, V) or by a valid pulse and a zero (B, 0, V).
A BPV with the same polarity as the last BPV.
The fourth zero in an EXZ occurrence (only in hardware mode or when ITU = 0).
A BPV with the same polarity as the last BPV.
Figure
register (CPU bus mode).
RCVH
8-1.
and RCVL. The value of the internal counter is latched into the RCVH/RCVL register and
RCR
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register.
Table
RCR