PIC18F2420-I/SP Microchip Technology Inc., PIC18F2420-I/SP Datasheet - Page 265
PIC18F2420-I/SP
Manufacturer Part Number
PIC18F2420-I/SP
Description
28 Pin, 16 KB Flash, 768 RAM, 25 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F2420-ISP.pdf
(388 pages)
Specifications of PIC18F2420-I/SP
A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
16K Bytes
Ram Size
768 Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2420-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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ANDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2003 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
REG
W
REG
Q1
=
=
=
=
register ‘f’
AND W with f
[ label ] ANDWF
0
d
a
(W) .AND. (f)
N, Z
The contents of W are AND’ed with
register ‘f’. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank will be
selected. If ‘a’ is ‘1’, the BSR will
not be overridden (default).
1
1
ANDWF
Read
0001
Q2
0x17
0xC2
0x02
0xC2
f
[0,1]
[0,1]
255
01da
REG, W
Process
Data
Q3
dest
ffff
f [,d [,a]]
destination
Write to
PIC18F2220/2320/4220/4320
Q4
ffff
BC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
No
PC
If Carry
If Carry
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Carry
[ label ] BC
-128
if carry bit is ’1’
(PC) + 2 + 2n
None
If the Carry bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
Q2
‘n’
‘n’
=
=
=
=
=
n
address (HERE)
1;
address (JUMP)
0;
address (HERE+2)
127
0010
operation
BC
Process
Process
Data
Data
n
No
Q3
Q3
DS39599C-page 263
PC
JUMP
nnnn
Write to PC
operation
operation
No
No
Q4
Q4
nnnn
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