PIC18F2420-I/SP Microchip Technology Inc., PIC18F2420-I/SP Datasheet - Page 294
PIC18F2420-I/SP
Manufacturer Part Number
PIC18F2420-I/SP
Description
28 Pin, 16 KB Flash, 768 RAM, 25 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F2420-ISP.pdf
(388 pages)
Specifications of PIC18F2420-I/SP
A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
16K Bytes
Ram Size
768 Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2420-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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PIC18F2220/2320/4220/4320
SUBWFB
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
DS39599C-page 292
Q Cycle Activity:
Decode
Q1
register ‘f’
Subtract W from f with Borrow
[ label ] SUBWFB
0
d
a
(f) – (W) – (C)
N, OV, C, DC, Z
Subtract W and the carry flag (bor-
row) from register ‘f’ (2’s complement
method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default). If
‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If
‘a’ is ‘1’, then the bank will be
selected as per the BSR value
(default).
1
1
Read
0101
Q2
f
[0,1]
[0,1]
255
10da
Process
Data
Q3
dest
ffff
f [,d [,a]]
destination
Write to
Q4
ffff
Example 1:
Example 2:
Example 3:
Before Instruction
After Instruction
Before Instruction
After Instruction
Before Instruction
After Instruction
REG
W
C
REG
W
C
Z
N
REG
W
C
REG
W
C
Z
N
REG
W
C
REG
W
C
Z
N
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
SUBWFB
SUBWFB REG, 0, 0
SUBWFB
0x19
0x0D
0x01
0x0C
0x0D
0x01
0x00
0x00
0x1B
0x1A
0x00
0x1B
0x00
0x01
0x01
0x00
0x03
0x0E
0x01
0xF5
0x0E
0x00
0x00
0x01
2003 Microchip Technology Inc.
REG, 1, 0
REG, 1, 0
(0001 1001)
(0000 1101)
(0000 1011)
(0000 1101)
; result is positive
(0001 1011)
(0001 1010)
(0001 1011)
; result is zero
(0000 0011)
(0000 1101)
(1111 0100)
; [2’s comp]
(0000 1101)
; result is negative
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