PIC16F777-I/P Microchip Technology Inc., PIC16F777-I/P Datasheet - Page 35

• Manufacturer Part Number: PIC16F777-I/P
• Description: 40 PIN, 14 KB FLASH, 368 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F777-I/P

• A/d Inputs: 14-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

4.2
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= ‘1’) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISB bit (= ‘0’) will
make the corresponding PORTB pin an output (i.e., put
the contents of the output latch on the selected pin).
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
FIGURE 4-3:
Four of the PORTB pins (RB7:RB4) have an inter-
rupt-on-change feature. Only pins configured as inputs
can cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the inter-
rupt-on-change comparison). The input pins (of
RB7:RB4) are compared with the old value latched on
the last read of PORTB. The “mismatch” outputs of
RB7:RB4 are ORed together to generate the RB Port
Change Interrupt with flag bit RBIF (INTCON<0>).
 2002 Microchip Technology Inc.
Note 1: I/O pins have diode protection to V
RBPU
Data Bus
WR Port
WR TRIS
RD TRIS
RD Port
RB0/INT
2: To enable weak pull-ups, set the appropriate TRIS
PORTB and the TRISB Register
(2)
bit(s) and clear the RBPU bit (OPTION_REG<7>).
TRIS Latch
Data Latch
D
D
CK
CK
Schmitt Trigger
Buffer
BLOCK DIAGRAM OF
RB3:RB0 PINS
Q
Q
Q
EN
TTL
Input
Buffer
D
DD
and V
V
RD Port
P
DD
SS
Weak
Pull-up
.
pin
I/O
(1)
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
This interrupt on mismatch feature, together with soft-
ware configureable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key depression. Refer to the Embedded
Control Handbook, “Implementing Wake-up on Key
Stroke” (AN552).
RB0/INT is an external interrupt input pin and is config-
ured using the INTEDG bit (OPTION_REG<6>).
RB0/INT is discussed in detail in Section 12.11.1.
FIGURE 4-4:
Note 1: I/O pins have diode protection to V
Set RBIF
RBPU
Data Bus
WR Port
WR TRIS
RD TRIS
RD Port
RB7:RB6 in Serial Programming mode
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
From other
RB7:RB4 pins
(2)
and clear the RBPU bit (OPTION_REG<7>).
Data Latch
TRIS Latch
D
D
CK
CK
Q
Q
BLOCK DIAGRAM OF
RB7:RB4 PINS
PIC16F7X
Q
Q
Latch
EN
EN
D
D
DD
DS30325B-page 33
TTL
Input
Buffer
and V
V
P
DD
SS
Weak
Pull-up
RD Port
.
Buffer
pin
I/O
Q1
Q3
ST
(1)