PIC16F777-I/P Microchip Technology Inc., PIC16F777-I/P Datasheet - Page 83

• Manufacturer Part Number: PIC16F777-I/P
• Description: 40 PIN, 14 KB FLASH, 368 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F777-I/P

• A/d Inputs: 14-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 10-9:
10.4.2
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP
mode. Bit SREN is a “don't care” in Slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
 2002 Microchip Technology Inc.
0Bh, 8Bh,
10Bh,18Bh
0Ch
18h
19h
8Ch
98h
99h
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
0Bh, 8Bh,
10Bh,18Bh
0Ch
18h
1Ah
8Ch
98h
99h
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices, always maintain these bits clear.
Address
Address
USART SYNCHRONOUS SLAVE
RECEPTION
INTCON
PIR1
RCSTA
TXREG
PIE1
TXSTA
SPBRG
INTCON
PIR1
RCSTA
RCREG
PIE1
TXSTA
SPBRG
Name
Name
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
USART Receive Register
Baud Rate Generator Register
USART Transmit Register
Baud Rate Generator Register
PSPIE
PSPIF
PSPIE
PSPIF
CSRC
SPEN
CSRC
SPEN
Bit 7
Bit 7
GIE
GIE
(1)
(1)
(1)
(1)
ADIE
Bit 6
PEIE
ADIF
RX9
PEIE
ADIF
ADIE
TX9
Bit 6
RX9
TX9
TMR0IE
TMR0IE
SREN
TXEN
RCIF
RCIE
Bit 5
SREN
TXEN
RCIF
RCIE
Bit 5
CREN ADDEN
SYNC
INTE
CREN ADDEN
SYNC
Bit 4
TXIF
TXIE
Bit 4
INTE
TXIF
TXIE
SSPIF
SSPIE
RBIE
SSPIE
Bit 3
SSPIF
RBIE
Bit 3
—
—
Follow these steps when setting up a Synchronous
Slave Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
TMR0IF
CCP1IE TMR2IE TMR1IE 0000 0000
CCP1IF TMR2IF
TMR0IF
CCP1IF TMR2IF TMR1IF 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000
BRGH
FERR
BRGH
Bit 2
FERR
Bit 2
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated, if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
bit CREN.
If using interrupts, ensure that GIE and PEIE in
the INTCON register are set.
OERR
TRMT
OERR
TRMT
INTF
Bit 1
Bit 1
INTF
TMR1IF 0000 0000
RX9D
TX9D
RX9D
TX9D
RBIF
RBIF
Bit 0
Bit 0
PIC16F7X
0000 000x
0000 000x
0000 0000
0000 -010
0000 0000
0000 000x
0000 000x
0000 0000
0000 -010
0000 0000
Value on:
Value on:
POR,
POR,
BOR
BOR
DS30325B-page 81
0000 000u
0000 0000
0000 000x
0000 0000
0000 0000
0000 -010
0000 0000
0000 000u
0000 0000
0000 000x
0000 0000
0000 0000
0000 -010
0000 0000
Value on
RESETS
all other
Value on
RESETS
all other