PIC18F2520-I/SO Microchip Technology Inc., PIC18F2520-I/SO Datasheet - Page 86
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PIC18F2520-I/SO
Manufacturer Part Number
PIC18F2520-I/SO
Description
28 Pin, 32 KB Flash, 1536 RAM, 25 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F2520-ISO.pdf
(390 pages)
Specifications of PIC18F2520-I/SO
A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SOIC
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC18F2420/2520/4420/4520
REGISTER 7-1:
DS39631A-page 84
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
EECON1 REGISTER
bit 7
EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access configuration registers
0 = Access Flash program or data EEPROM memory
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
0 = Perform write only
WRERR: Flash Program/Data EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any Reset during self-timed programming in
0 = The write operation completed
WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle
0 = Write cycle to the EEPROM is complete
RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit
S = Bit can be set by software, but not cleared
-n = Value at POR
EEPGD
R/W-x
Note:
(cleared by completion of erase operation)
normal operation, or an improper write attempt)
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)
When a WRERR occurs, the EEPGD and CFGS bits are not cleared.
This allows tracing of the error condition.
R/W-x
CFGS
U-0
Preliminary
—
W = Writable bit
‘1’ = Bit is set
R/W-0
FREE
WRERR
R/W-x
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
WREN
R/W-0
2004 Microchip Technology Inc.
x = Bit is unknown
R/S-0
WR
R/S-0
RD
bit 0
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