DS2181A+ Maxim Integrated Products, DS2181A+ Datasheet - Page 10

• Manufacturer Part Number: DS2181A+
• Description: IC TXRX CEPT PRIMARY RATE 40-DIP
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS2181A+

• Number Of Drivers/receivers: 1/1
• Protocol: CEPT
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Logic Type: CMOS
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• High Level Output Current: - 1 mA
• Interface: DMA, CPI
• Low Level Output Current: 4 mA
• Minimum Operating Temperature: 0 C
• Output Current: 4 mA
• Supply Current: 5 mA
• Supply Voltage Range: 4.5V To 5.5V
• Logic Case Style: LCC
• No. Of Pins: 44
• Operating Temperature Range: 0°C To +70°C
• Termination Type: SMD
• Transceiver Type: Network
• Driver Case Style: LCC
• Rohs Compliant: Yes
• Filter Terminals: SMD
• Interface Type: Serial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RCR: RECEIVE CONTROL REGISTER Figure 6
(MSB)
CEPT FRAME STRUCTURE
The CEPT frame is made up of 32 8-bit channels (time-slots) numbered from 0 to 31. The frame
alignment signal in bit positions 2 through 8 of timeslot 0 of every other frame is independent of the
various multiframe modes described below. Outputs TAF and RAF indicate frames which contain the
alignment signal. Timeslot 0 of frames not containing the frame alignment signal is used for alarm and
national data. See the separate DS2181A CEPT Transceiver Application Note for more details.
CAS SIGNALLING
CEPT networks support Channel Associated Signaling (CAS) or Common Channel Signaling (CCS).
These signaling modes are independently selectable for transmit and receive sides.
CAS (selected when TCR.5 = 0 and/or when RCR.5 = 0) is a bit-oriented signaling technique which
utilizes a 16-frame multiframe. The multiframe alignment signal (0-hex), extra and alarm bits occupy
timeslot 16 of frame 0. Timeslot 16 of the remaining 15 frames is reserved for channel signaling data.
Four signaling bits (A, B, C and D) are transmitted once per multiframe as shown in Figure 7. Input
TMSYNC establishes the transmitted CAS multiframe position. Signaling data can be sourced from input
TSD (TCR.6 = 1) or multiplexed into TSER (TCR.6 = 0).
SYMBOL
RESYNC
SYNCE
CMRC
CMSC
RSM
FRC
-
-
-
-
POSITION
RCR.7
RCR.6
RCR.5
RCR.4
RCR.3
RCR.2
RCR.1
RCR.0
RSM
NAME AND DESCRIPTION
Reserved; must be 0 for proper operation.
Reserved; must be 0 for proper operation.
Received Signaling Mode
0 = Channel Associated Signaling (CAS).
1 = Common Channel Signaling (CCS).
CAS Multiframe Sync Criteria
0 = Declare sync when fixed sync criteria met.
1 = Declare sync when fixed criteria are met and two additional
consecutive valid multiframe alignment signals are detected.
CAS Multiframe Resync Criteria
0 = Utilize only fixed resync criteria.
1 = Resync if fixed criteria met and/or if two consecutive timeslot
16 words have values of 0 in the first four MSB positions
(0000xxxx).
Frame Resync Criteria
0 = Utilize only fixed resync criteria.
1 = Resync if fixed criteria met and/or if bit 2 in timeslot 0 of non-
align frames is received in error on three consecutive occasions.
Sync Enable
If clear, the synchronizer will automatically begin resync if error
criteria are met. If high, no auto resync occurs.
Resync
When toggled low to high, the receive synchronizer will initiate
immediately.
subsequent resyncs.
CMSC
10 of 32
The bit must be cleared, then set again for
CMRC
FRC
SYNCE
RESYNC
(LSB)
DS2181A