DS2181A+ Maxim Integrated Products, DS2181A+ Datasheet - Page 16

• Manufacturer Part Number: DS2181A+
• Description: IC TXRX CEPT PRIMARY RATE 40-DIP
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS2181A+

• Number Of Drivers/receivers: 1/1
• Protocol: CEPT
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Logic Type: CMOS
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• High Level Output Current: - 1 mA
• Interface: DMA, CPI
• Low Level Output Current: 4 mA
• Minimum Operating Temperature: 0 C
• Output Current: 4 mA
• Supply Current: 5 mA
• Supply Voltage Range: 4.5V To 5.5V
• Logic Case Style: LCC
• No. Of Pins: 44
• Operating Temperature Range: 0°C To +70°C
• Termination Type: SMD
• Transceiver Type: Network
• Driver Case Style: LCC
• Rohs Compliant: Yes
• Filter Terminals: SMD
• Interface Type: Serial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS2181A
TRANSMIT MULTIFRAME BOUNDARY TIMING Figure 13
NOTES:
1. Low-high transitions on TMSYNC and/or TFSYNC must occur one TCLK period early with respect
to actual frame and multiframe boundaries. TMO follows the rising edge of TMSYNC or TFSYNC.
2. TAF transitions on true frame boundaries.
3. Delay from TSER to TPOS, TNEG is five TCLK periods.
TRANSMIT SIGNALING TIMESLOT TIMING Figure 14
RECEIVE SIGNALING
Receive signaling data is available at two outputs: RSER and RSD. RSER outputs the signaling data in
timeslot 16 at RSER. The signaling data is also extracted from timeslot 16 and presented at RSD during
the timeslots shown in Table 7. This channel-associated signaling simplifies CAS system design.
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