PIC16F54-I/P Microchip Technology Inc., PIC16F54-I/P Datasheet - Page 35

• Manufacturer Part Number: PIC16F54-I/P
• Description: 18 PIN, 768 B FLASH, 25 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F54-I/P

• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Frequency: 20 MHz
• Input Output: 12
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 750 Bytes
• Ram Size: 25 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

7.0
The Timer0 module has the following features:
• 8-bit Timer/Counter register, TMR0
• 8-bit software programmable prescaler
• Internal or external clock select
Figure 7-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In Timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 7-2 and Figure 7-3).
The user can work around this by writing an adjusted
value to the TMR0 register.
FIGURE 7-1:
FIGURE 7-2:
 2004 Microchip Technology Inc.
- Readable and writable
- Edge select for external clock
Instruction
Timer0
Note 1:
PC
(Program
Counter)
Fetch
Instruction
Executed
T0CKI
pin
2:
TIMER0 MODULE AND TMR0
REGISTER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T0
Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in Section 3.4 “Option Register”.
The prescaler is shared with the Watchdog Timer (Figure 7-5).
T0SE(1)
PC - 1
F
OSC
TIMER0 BLOCK DIAGRAM
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
/4
T0 + 1
PC
T0CS(1)
0
1
T0 + 2
Write TMR0
executed
PC + 1
PS2, PS1, PS0(1)
Programmable
Prescaler(2)
NT0
Read TMR0
reads NT0
3
PC + 2
Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
incrementing edge is determined by the source edge
select bit T0SE (OPTION<4>). Clearing the T0SE bit
selects the rising edge. Restrictions on the external
clock input are discussed in detail in Section 7.1
“Using Timer0 with an External Clock”.
The prescaler assignment is controlled in software by
the control bit PSA (OPTION<3>). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4,...,
1:256 are selectable. Section 7.2 “Prescaler” details
the operation of the prescaler.
A summary of registers associated with the Timer0
module is found in Table 7-1.
PSA(1)
Read TMR0
reads NT0
NT0
Note:
1
0
PC + 3
PSout
The prescaler may be used by either the
Timer0 module or the Watchdog Timer, but
not both.
(2 cycle delay)
Read TMR0
reads NT0
NT0
Sync with
Internal
PC + 4
Clocks
Read TMR0
reads NT0 + 1
NT0 + 1
PIC16F5X
PSout
Sync
PC + 5
DS41213C-page 33
TMR0 reg
Data Bus
Read TMR0
reads NT0 + 2
NT0 + 2
PC + 6
8