PIC18F2520-I/ML Microchip Technology Inc., PIC18F2520-I/ML Datasheet - Page 294
PIC18F2520-I/ML
Manufacturer Part Number
PIC18F2520-I/ML
Description
28 QFN 6x6mm TUBE, 32 KB Flash, 1536 RAM, 25 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F2520-IML.pdf
(412 pages)
Specifications of PIC18F2520-I/ML
A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
1K Bytes
Input Output
25
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin QFN
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Temperature Range
–40 to 125 °C
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2520-I/ML
Manufacturer:
MICROCHI
Quantity:
20 000
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PIC18F2420/2520/4420/4520
MOVFF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (source)
2nd word (destin.)
Description:
Words:
Cycles:
Example:
DS39631E-page 292
Q Cycle Activity:
Before Instruction
After Instruction
Decode
Decode
REG1
REG2
REG1
REG2
Q1
No dummy
register ‘f’
operation
Move f to f
MOVFF f
0 ≤ f
0 ≤ f
(f
None
The contents of source register ‘f
moved to destination register ‘f
Location of source ‘f
in the 4096-byte data space (000h to
FFFh) and location of destination ‘f
can also be anywhere from 000h to
FFFh.
Either source or destination can be W
(a useful special situation).
MOVFF
transferring a data memory location to a
peripheral register (such as the transmit
buffer or an I/O port).
The MOVFF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
2
2 (3)
MOVFF
s
Read
) → f
(src)
read
1100
1111
Q2
No
=
=
=
=
s
d
≤ 4095
≤ 4095
d
is particularly useful for
33h
11h
33h
33h
s
REG1, REG2
,f
ffff
ffff
d
operation
Process
Data
Q3
No
s
’ can be anywhere
ffff
ffff
register ‘f’
operation
(dest)
Write
d
Q4
No
fff
fff
’.
s
’ are
d
f
f
’
s
d
MOVLB
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
BSR Register =
BSR Register =
Q1
Move Literal to Low Nibble in BSR
MOVLW k
0 ≤ k ≤ 255
k →
None
The 8-bit literal ‘k’ is loaded into the
Bank Select Register (BSR). The value
of BSR<7:4> always remains ‘
regardless of the value of k
1
1
MOVLB
literal ‘k’
Read
0000
Q2
BSR
© 2008 Microchip Technology Inc.
02h
05h
0001
5
Process
Data
Q3
kkkk
Write literal
7
‘k’ to BSR
:k
4
0
.
Q4
’,
kkkk
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