PIC18F4220-I/P Microchip Technology Inc., PIC18F4220-I/P Datasheet - Page 177

• Manufacturer Part Number: PIC18F4220-I/P
• Description: Microcontroller; 4 KB Flash; 512 RAM; 256 EEPROM; 36 I/O; 40-Pin-PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4220-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 4K Bytes
• Ram Size: 512 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

17.4.4.5
The SEN bit is also used to synchronize writes to the
CKP bit. If a user clears the CKP bit, the SCL output is
forced to ‘0’. When the SEN bit is set to ‘1’, setting the
CKP bit will not assert the SCL output low until the
SCL output is already sampled low. If the user
attempts to drive SCL low, the CKP bit will not assert
the SCL line until an external I
already asserted the SCL line. The SCL output will
FIGURE 17-12:
 2003 Microchip Technology Inc.
WR
SSPCON1
SDA
SCL
CKP
Clock Synchronization and
the CKP bit (SEN = 1)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLOCK SYNCHRONIZATION TIMING
2
C master device has
DX
PIC18F2220/2320/4220/4320
Master device
asserts clock
remain low until the CKP bit is set and all other
devices on the I
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure 17-12).
Note:
Master device
deasserts clock
If the SEN bit is ‘0’, clearing the CKP bit
will result in immediately driving the SCL
output to ‘0’ regardless of the current
state.
2
C bus have deasserted SCL. This
DS39599C-page 175
DX-1