PIC18F4220-I/P Microchip Technology Inc., PIC18F4220-I/P Datasheet - Page 261
PIC18F4220-I/P
Manufacturer Part Number
PIC18F4220-I/P
Description
Microcontroller; 4 KB Flash; 512 RAM; 256 EEPROM; 36 I/O; 40-Pin-PDIP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F4220-IP.pdf
(388 pages)
Specifications of PIC18F4220-I/P
A/d Inputs
13-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
4K Bytes
Ram Size
512 Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4220-I/PT
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SST
Quantity:
1 150
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PIC18F4220-I/PT
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TABLE 24-2:
2003 Microchip Technology Inc.
CONTROL OPERATIONS
BC
BN
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
CALL
CLRWDT
DAW
GOTO
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
RETLW
RETURN
SLEEP
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
Mnemonic,
Operands
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
if assigned.
second cycle is executed as a NOP.
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
n
n
n
n
n
n
n
n
n
n, s
—
—
n
—
—
—
—
n
s
k
s
—
PIC18FXXX INSTRUCTION SET (CONTINUED)
Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call subroutine 1st word
Clear Watchdog Timer
Decimal Adjust WREG
Go to address 1st word
No Operation
No Operation (Note 4)
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device Reset
Return from interrupt enable
Return with literal in WREG
Return from Subroutine
Go into Standby mode
Description
2nd word
2nd word
PIC18F2220/2320/4220/4320
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
2
1
1
2
1
1
1
1
2
1
2
2
2
1
Cycles
1110
1110
1110
1110
1110
1110
1110
1101
1110
1110
1111
0000
0000
1110
1111
0000
1111
0000
0000
1101
0000
0000
0000
0000
0000
MSb
16-Bit Instruction Word
0010
0110
0011
0111
0101
0001
0100
0nnn
0000
110s
kkkk
0000
0000
1111
kkkk
0000
xxxx
0000
0000
1nnn
0000
0000
1100
0000
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
kkkk
0001
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0100
0111
kkkk
kkkk
0000
xxxx
0110
0101
nnnn
1111
000s
kkkk
001s
0011
LSb
None
None
None
None
None
None
None
None
None
None
TO
C, DC
None
None
None
None
None
None
All
GIE/GIEH,
PEIE/GIEL
None
None
TO
,
,
Affected
PD
PD
DS39599C-page 259
Status
Notes
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