PIC18F45J10-I/ML Microchip Technology Inc., PIC18F45J10-I/ML Datasheet - Page 190

• Manufacturer Part Number: PIC18F45J10-I/ML
• Description: 44 PIN, 32 KB FLASH, 1024 RAM
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45J10-I/ML

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 32
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 2-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F45J10 FAMILY
REGISTER 16-1:
DS39682B-page 188
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care.
BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode.
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Legend:
R = Readable bit
-n = Value at POR
CSRC
R/W-0
Note:
SREN/CREN overrides TXEN in Sync mode.
R/W-0
TX9
R/W-0
TXEN
Preliminary
‘1’ = Bit is set
W = Writable bit
R/W-0
SYNC
SENDB
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
BRGH
© 2006 Microchip Technology Inc.
x = Bit is unknown
TRMT
R-1
R/W-0
TX9D
bit 0