PIC18F45J10-I/ML Microchip Technology Inc., PIC18F45J10-I/ML Datasheet - Page 329
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC18F45J10-I/ML
Manufacturer Part Number
PIC18F45J10-I/ML
Description
44 PIN, 32 KB FLASH, 1024 RAM
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F45J10-IML.pdf
(359 pages)
Specifications of PIC18F45J10-I/ML
A/d Inputs
13-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
0 Bytes
Input Output
32
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin QFN
Programmable Memory
32K Bytes
Ram Size
1K Bytes
Speed
40 MHz
Timers
1-8 bit, 2-16 bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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TABLE 23-25: A/D CONVERSION REQUIREMENTS
© 2006 Microchip Technology Inc.
130
131
132
135
Legend: TBD = To Be Determined
Note 1:
Param
No.
2:
3:
4:
T
T
T
T
Symbol
AD
CNV
ACQ
SWC
The time of the A/D clock period is dependent on the device frequency and the T
ADRES registers may be read on the following T
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
On the following cycle of the device clock.
A/D Clock Period
Conversion Time
(not including acquisition time) (Note 2)
Acquisition Time (Note 3)
Switching Time from Convert → Sample
Characteristic
DD
to V
SS
or V
SS
Preliminary
to V
DD
). The source impedance (R
CY
PIC18F45J10 FAMILY
cycle.
TBD
TBD
Min
0.7
1.4
11
—
(Note 4)
25.0
Max
12
—
—
1
(1)
Units
T
μs
μs
μs
μs
AD
S
) on the input channels is 50Ω.
T
A/D RC mode
-40°C to +85°C
0°C ≤ to ≤ +85°C
OSC
AD
based, V
clock divider.
Conditions
DS39682B-page 327
REF
≥ 2.0V
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