PIC18F4620-E/P Microchip Technology Inc., PIC18F4620-E/P Datasheet - Page 380

• Manufacturer Part Number: PIC18F4620-E/P
• Description: 40 Pin, 64 KB Flash, 3968 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4620-E/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 36
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 64K Bytes
• Ram Size: 4K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2525/2620/4525/4620
Flash Program Memory ...................................................... 73
FSCM. See Fail-Safe Clock Monitor.
G
GOTO ............................................................................... 288
H
Hardware Multiplier ............................................................ 89
High/Low-Voltage Detect ................................................. 243
HLVD. See High/Low-Voltage Detect. ............................. 243
I
I/O Ports ........................................................................... 105
I
DS39626B-page 378
2
C Mode (MSSP)
Associated Registers ................................................. 81
Control Registers ....................................................... 74
Erase Sequence ........................................................ 78
Erasing ....................................................................... 78
Operation During Code-Protect ................................. 81
Reading ...................................................................... 77
Table Pointer
Table Pointer Boundaries .......................................... 76
Table Reads and Table Writes .................................. 73
Write Sequence ......................................................... 79
Writing ........................................................................ 79
Introduction ................................................................ 89
Operation ................................................................... 89
Performance Comparison .......................................... 89
Applications .............................................................. 246
Associated Registers ............................................... 247
Characteristics ......................................................... 340
Current Consumption ............................................... 245
Effects of a Reset ..................................................... 247
Operation ................................................................. 244
Setup ........................................................................ 245
Start-up Time ........................................................... 245
Typical Application ................................................... 246
Acknowledge Sequence Timing ............................... 194
Baud Rate Generator ............................................... 187
Bus Collision
Clock Arbitration ....................................................... 188
Clock Stretching ....................................................... 180
Clock Synchronization and the
Effects of a Reset ..................................................... 195
General Call Address Support ................................. 184
I
2
C Clock Rate w/BRG ............................................. 187
EECON1 and EECON2 ..................................... 74
TABLAT (Table Latch) Register ......................... 76
TBLPTR (Table Pointer) Register ...................... 76
Boundaries Based on Operation ........................ 76
Operations with TBLRD
Protection Against Spurious Writes ................... 81
Unexpected Termination .................................... 81
Write Verify ........................................................ 81
During Sleep .................................................... 247
During a Repeated Start
During a Start Condition ................................... 196
During a Stop Condition ................................... 199
10-Bit Slave Receive Mode (SEN = 1) ............. 180
10-Bit Slave Transmit Mode ............................. 180
7-Bit Slave Receive Mode (SEN = 1) ............... 180
7-Bit Slave Transmit Mode ............................... 180
CKP bit (SEN = 1) ............................................ 181
and TBLWT (table) .................................... 76
Condition .................................................. 198
Preliminary
ID Locations ............................................................. 249, 266
INCF ................................................................................ 288
INCFSZ ............................................................................ 289
In-Circuit Debugger .......................................................... 266
In-Circuit Serial Programming (ICSP) ...................... 249, 266
Indexed Literal Offset Addressing
Indexed Literal Offset Mode ............................................. 314
Indirect Addressing ............................................................ 68
INFSNZ ............................................................................ 289
Initialization Conditions for all Registers ...................... 49–52
Instruction Cycle ................................................................ 57
Instruction Flow/Pipelining ................................................. 57
Instruction Set .................................................................. 267
Master Mode ............................................................ 185
Multi-Master Communication, Bus Collision
Multi-Master Mode ................................................... 195
Operation ................................................................. 174
Read/Write Bit Information (R/W Bit) ............... 174, 175
Registers ................................................................. 170
Serial Clock (RC3/SCK/SCL) ................................... 175
Slave Mode .............................................................. 174
Sleep Operation ....................................................... 195
Stop Condition Timing ............................................. 194
and Standard PIC18 Instructions ............................. 314
Clocking Scheme ....................................................... 57
ADDLW .................................................................... 273
ADDWF .................................................................... 273
ADDWF (Indexed Literal Offset Mode) .................... 315
ADDWFC ................................................................. 274
ANDLW .................................................................... 274
ANDWF .................................................................... 275
BC ............................................................................ 275
BCF ......................................................................... 276
BN ............................................................................ 276
BNC ......................................................................... 277
BNN ......................................................................... 277
BNOV ...................................................................... 278
BNZ ......................................................................... 278
BOV ......................................................................... 281
BRA ......................................................................... 279
BSF .......................................................................... 279
BSF (Indexed Literal Offset Mode) .......................... 315
BTFSC ..................................................................... 280
BTFSS ..................................................................... 280
BTG ......................................................................... 281
BZ ............................................................................ 282
CALL ........................................................................ 282
CLRF ....................................................................... 283
CLRWDT ................................................................. 283
COMF ...................................................................... 284
CPFSEQ .................................................................. 284
CPFSGT .................................................................. 285
CPFSLT ................................................................... 285
DAW ........................................................................ 286
DCFSNZ .................................................................. 287
DECF ....................................................................... 286
Operation ......................................................... 186
Reception ........................................................ 191
Repeated Start Condition Timing .................... 190
Start Condition Timing ..................................... 189
Transmission ................................................... 191
and Arbitration ................................................. 195
Addressing ....................................................... 174
Reception ........................................................ 175
Transmission ................................................... 175
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