PIC16F877-04I/P Microchip Technology Inc., PIC16F877-04I/P Datasheet - Page 23
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PIC16F877-04I/P
Manufacturer Part Number
PIC16F877-04I/P
Description
40 PIN, 7 KB FLASH, 368 RAM, 33 I/O, PDIP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F877-04IP.pdf
(218 pages)
Specifications of PIC16F877-04I/P
A/d Inputs
8-Channel, 10-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Frequency
20 MHz
Input Output
33
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
14K Bytes
Ram Size
368 Bytes
Serial Interface
MSSP, USART
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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2.2.2.4
The PIE1 register contains the individual enable bits for
the peripheral interrupts.
REGISTER 2-4:
2001 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PIE1 Register
PIE1 REGISTER (ADDRESS 8Ch)
PSPIE
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Note 1: PSPIE is reserved on PIC16F873/876 devices; always maintain this bit clear.
bit 7
Legend:
R = Readable bit
- n = Value at POR
PSPIE
R/W-0
(1)
(1)
: Parallel Slave Port Read/Write Interrupt Enable bit
R/W-0
ADIE
R/W-0
RCIE
W = Writable bit
’1’ = Bit is set
R/W-0
TXIE
Note:
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
SSPIE
R/W-0
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
CCP1IE
R/W-0
PIC16F87X
x = Bit is unknown
TMR2IE
R/W-0
DS30292C-page 21
TMR1IE
R/W-0
bit 0