PIC16F877-04I/P Microchip Technology Inc., PIC16F877-04I/P Datasheet - Page 80
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PIC16F877-04I/P
Manufacturer Part Number
PIC16F877-04I/P
Description
40 PIN, 7 KB FLASH, 368 RAM, 33 I/O, PDIP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F877-04IP.pdf
(218 pages)
Specifications of PIC16F877-04I/P
A/d Inputs
8-Channel, 10-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Frequency
20 MHz
Input Output
33
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
14K Bytes
Ram Size
368 Bytes
Serial Interface
MSSP, USART
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC16F87X
9.2.5
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET, or when the MSSP module is
disabled. Control of the I
P bit is set, or the bus is idle, with both the S and P bits
clear.
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
FIGURE 9-9:
9.2.6
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET or
when the MSSP module is disabled. Control of the I
bus may be taken when bit P (SSPSTAT<4>) is set, or
the bus is idle with both the S and P bits clear. When
the bus is busy, enabling the SSP Interrupt will gener-
ate the interrupt when the STOP condition occurs.
DS30292C-page 78
SDA
SCL
MASTER MODE
MULTI-MASTER MODE
SSP BLOCK DIAGRAM (I
2
C bus may be taken when the
SDA in
SCL in
Bus Collision
Read
MSb
START bit, STOP bit,
Write Collision Detect
START bit Detect,
end of XMIT/RCV
State Counter for
Clock Arbitration
STOP bit Detect
2
Acknowledge
2
C
SSPBUF
C MASTER MODE)
Generate
SSPSR
LSb
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (an SSP interrupt will occur if
enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated START
In Multi-Master operation, the SDA line must be moni-
tored for arbitration to see if the signal level is the
expected output level. This check is performed in hard-
ware, with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A START Condition
• A Repeated START Condition
• An Acknowledge Condition
Write
Clock
Data Bus
Shift
Internal
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
2001 Microchip Technology Inc.
SSPADD<6:0>
SSPM3:SSPM0,
Baud
Rate
Generator