PIC16F877-04I/P Microchip Technology Inc., PIC16F877-04I/P Datasheet - Page 49
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PIC16F877-04I/P
Manufacturer Part Number
PIC16F877-04I/P
Description
40 PIN, 7 KB FLASH, 368 RAM, 33 I/O, PDIP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F877-04IP.pdf
(218 pages)
Specifications of PIC16F877-04I/P
A/d Inputs
8-Channel, 10-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Frequency
20 MHz
Input Output
33
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
14K Bytes
Ram Size
368 Bytes
Serial Interface
MSSP, USART
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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5.0
The Timer0 module timer/counter has the following fea-
tures:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 5-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
Additional information on the Timer0 module is avail-
able in the PICmicro™ Mid-Range MCU Family Refer-
ence Manual (DS33023).
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0 mod-
ule will increment every instruction cycle (without pres-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
FIGURE 5-1:
2001 Microchip Technology Inc.
RA4/T0CKI
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
CLKOUT (= F
WDT Enable bit
pin
Watchdog
TIMER0 MODULE
Timer
OSC
/4)
T0SE
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
0
1
PSA
M
U
X
0
1
T0CS
M
U
X
0
8-bit Prescaler
8 - to - 1MUX
Time-out
8
M U X
WDT
PRESCALER
1
0
1
PSA
M
U
X
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment either on every rising, or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed in detail in Section 5.2.
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The pres-
caler is not readable or writable. Section 5.3 details the
operation of the prescaler.
5.1
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module Interrupt Ser-
vice Routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP, since the timer is shut-off during SLEEP.
PSA
Timer0
PS2:PS0
Timer0 Interrupt
Cycles
SYNC
2
Source
Edge
PIC16F87X
TMR0 Reg
Data Bus
Select
8
DS30292C-page 47
Set Flag Bit T0IF
on Overflow
bit,
T0SE