PIC18F1220-I/SO Microchip Technology Inc., PIC18F1220-I/SO Datasheet - Page 73
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PIC18F1220-I/SO
Manufacturer Part Number
PIC18F1220-I/SO
Description
Microcontroller; 4 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-SOIC
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F1220-ISO.pdf
(310 pages)
Specifications of PIC18F1220-I/SO
A/d Inputs
7-Channel, 10-Bit
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
16
Interface
USART
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin SOIC
Programmable Memory
4K Bytes
Ram Size
256 Bytes
Speed
20 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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8.0
8.1
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18F1220/1320 devices. By making the multiply
a hardware operation, it completes in a single instruc-
tion cycle. This is an unsigned multiply that gives a
16-bit result. The result is stored into the 16-bit product
register pair (PRODH:PRODL). The multiplier does not
affect any flags in the Status register.
TABLE 8-1:
8.2
Example 8-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 8-1:
2004 Microchip Technology Inc.
8 x 8 unsigned
8 x 8 signed
16 x 16 unsigned
16 x 16 signed
MOVF
MULWF
Routine
8 x 8 HARDWARE MULTIPLIER
Introduction
Operation
ARG1, W
ARG2
PERFORMANCE COMPARISON
8 x 8 UNSIGNED
MULTIPLY ROUTINE
Without hardware multiply
Without hardware multiply
Without hardware multiply
Without hardware multiply
;
; ARG1 * ARG2 ->
; PRODH:PRODL
Hardware multiply
Hardware multiply
Hardware multiply
Hardware multiply
Multiply Method
Program
Memory
(Words)
13
33
21
28
52
35
1
6
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 8-1 shows a performance comparison between
Enhanced devices using the single-cycle hardware
multiply and performing the same function without the
hardware multiply.
EXAMPLE 8-2:
MOVF
MULWF
BTFSC
SUBWF
MOVF
BTFSC
SUBWF
algorithms
Cycles
(Max)
242
254
69
91
28
40
1
6
PIC18F1220/1320
ARG1, W
ARG2
ARG2, SB
PRODH, F
ARG2, W
ARG1, SB
PRODH, F
@ 40 MHz
24.2 s
25.4 s
100 ns
600 ns
6.9 s
9.1 s
2.8 s
4 s
8 x 8 SIGNED MULTIPLY
ROUTINE
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
;
; Test Sign Bit
; PRODH = PRODH
;
@ 10 MHz
102.6 s
27.6 s
36.4 s
96.8 s
11.2 s
Time
400 ns
2.4 s
16 s
- ARG1
- ARG2
DS39605C-page 71
@ 4 MHz
242 s
254 s
69 s
91 s
28 s
40 s
1 s
6 s
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