PIC10F202-I/P Microchip Technology Inc., PIC10F202-I/P Datasheet - Page 41
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PIC10F202-I/P
Manufacturer Part Number
PIC10F202-I/P
Description
8 PIN, 768 B FLASH, 24 RAM, 4 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC10F202-IP.pdf
(88 pages)
Specifications of PIC10F202-I/P
Cpu Speed
1 MIPS
Eeprom Memory
0 Bytes
Frequency
4 MHz
Input Output
4
Memory Type
Flash
Number Of Bits
8
Package Type
8-pin PDIP
Programmable Memory
750 Bytes
Ram Size
24 Bytes
Speed
4 MHz
Timers
1-8-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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Quantity
Price
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Manufacturer:
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8.2
A single comparator is shown in Figure 8-2 along with
the relationship between the analog input levels and
the digital output. When the analog input at V
than the analog input V
is a digital low level. When the analog input at V
greater than the analog input V
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 8-2 represent
the uncertainty due to input offsets and response time.
See Table 12-2 for Common Mode Voltage.
FIGURE 8-2:
8.3
An internal reference signal may be used depending on
the comparator operating mode. The analog signal that
is present at V
the digital output of the comparator is adjusted
accordingly (Figure 8-2). Please see Table 12-2 for
internal reference specifications.
8.4
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output is to have a valid level. If the com-
parator inputs are changed, a delay must be used to
allow the comparator to settle to its new state. Please
see
specifications.
© 2006 Microchip Technology Inc.
V
V
Result
IN
IN
-
+
Table 12-2
Vin+
Vin-
Comparator Operation
Comparator Reference
Comparator Response Time
IN
- is compared to the signal at V
for
+
–
SINGLE COMPARATOR
IN
comparator
-, the output of the comparator
IN
-, the output of the
response
Result
IN
+ is less
IN
+ and
IN
time
+ is
Preliminary
PIC10F200/202/204/206
8.5
The comparator output is read through CMCON0
register. This bit is read-only. The comparator output
may also be used internally, see Figure 8-1.
8.6
The comparator wake-up flag is set whenever all of the
following conditions are met:
• CWU = 0 (CMCON0<0>)
• CMCON0 has been read to latch the last known
• Device is in Sleep
• The output of the comparator has changed state
The wake-up flag may be cleared in software or by
another device Reset.
8.7
When the comparator is active and the device is placed
in Sleep mode, the comparator remains active. While
the comparator is powered-up, higher Sleep currents
than shown in the power-down current specification will
occur. To minimize power consumption while in Sleep
mode, turn off the comparator before entering Sleep.
8.8
A Power-on Reset (POR) forces the CMCON0 register
to its Reset state. This forces the Comparator module
to be in the comparator Reset mode. This ensures that
all potential inputs are analog inputs. Device current is
minimized when analog inputs are present at Reset
time. The comparator will be powered-down during the
Reset interval.
8.9
A simplified circuit for an analog input is shown in
Figure 8-3. Since the analog pins are connected to a
digital output, they have reverse biased diodes to V
and V
V
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
maximum
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
SS
Note:
state of the CMPOUT bit (MOVF CMCON0, W)
and V
SS
. The analog input therefore, must be between
Comparator Output
Comparator Wake-up Flag
Comparator Operation During
Sleep
Effects of a Reset
Analog Input Connection
Considerations
DD
Analog levels on any pin that is defined as
a digital input may cause the input buffer to
consume more current than is specified.
source
. If the input voltage deviates from this
impedance
DS41239C-page 39
of
10 k
DD
is