ISP1506BBS-T ST-Ericsson Inc, ISP1506BBS-T Datasheet - Page 15

• Manufacturer Part Number: ISP1506BBS-T
• Description: IC ULPI TRANSCEIVER 24-HVQFN
• Manufacturer: ST-Ericsson Inc
• Type: Transceiverr

Specifications of ISP1506BBS-T

• Number Of Drivers/receivers: 1/1
• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
8. Modes of operation
Table 4.
ISP1506A_ISP1506B_1
Product data sheet
Signal name
CLOCK
DATA[3:0]
ULPI signal description
Direction on
ISP1506
I/O
I/O
8.1.1 Synchronous mode
8.1 ULPI modes
The ISP1506 ULPI bus can be programmed to operate in three modes. Each mode
reconfigures the signals on the data bus as described in the following subsections. Setting
more than one mode will lead to undefined behavior.
This is default mode. At power-up, and when CLOCK is stable, the ISP1506 will enter
synchronous mode. The link must synchronize all ULPI signals to CLOCK, meeting the
set-up and hold times as defined in
synchronous mode is given in
This mode is used by the link to perform the following tasks:
For more information on the various synchronous mode protocols, see
•
•
•
•
High-speed detection handshake (chirp)
Transmit and receive USB packets
Read and write to registers
Receive USB status updates (RXCMDs)
Signal description
60 MHz interface clock. If a crystal is attached or a clock is driven into the XTAL1 pin, the
ISP1506 will drive a 60 MHz output clock.
4-bit data bus. In synchronous mode, the link drives DATA[3:0] to LOW by default. The link
initiates transfers by sending a nonzero data pattern called TXCMD (transmit command). In
synchronous mode, the direction of DATA[3:0] is controlled by DIR. Contents of DATA[3:0]
lines must be ignored for exactly one clock cycle whenever DIR changes value. This is called
the turnaround cycle. Bytes of data are transferred between the link and PHY in 4-bit nibbles.
The least significant nibble, DATA[3:0], is transferred first on the rising edge of clock. The
most significant nibble, DATA[7:4], is transferred next on the falling edge of clock. Transferring
an odd number of 4-bit nibbles is not allowed.
Data lines have fixed direction and different meaning in low-power and 3-pin serial modes.
Rev. 01 — 30 May 2007
Table
Section
4.
15. A description of the ULPI pin behavior in
ISP1506A; ISP1506B
ULPI HS USB OTG transceiver
© NXP B.V. 2007. All rights reserved.
Section
9.
15 of 79