ISP1506BBS-T ST-Ericsson Inc, ISP1506BBS-T Datasheet - Page 46

• Manufacturer Part Number: ISP1506BBS-T
• Description: IC ULPI TRANSCEIVER 24-HVQFN
• Manufacturer: ST-Ericsson Inc
• Type: Transceiverr

Specifications of ISP1506BBS-T

• Number Of Drivers/receivers: 1/1
• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 25.
Table 26.
ISP1506A_ISP1506B_1
Product data sheet
Bit
7
6
5
4 to 3
2
1 to 0
Bit
Symbol
Reset
Access
Symbol
-
SUSPENDM
RESET
OPMODE
[1:0]
TERMSELECT
XCVRSELECT
[1:0]
Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit description
Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit allocation
PROT_DIS
10.1.3 Interface Control register
R/W/S/C
INTF_
7
0
The Interface Control register enables alternative interfaces. All of these modes are
optional features provided for legacy link cores. Setting more than one of these fields
results in undefined behavior.
Description
reserved
Suspend LOW: Active LOW PHY suspend.
Places the PHY into low-power mode. The PHY will power down all blocks, except the full-speed
receiver, OTG comparators and ULPI interface pins.
To come out of low-power mode, the link must assert STP. The PHY will automatically clear this
bit when it exits low-power mode.
0b — Low-power mode
1b — Powered (default)
Reset: Active HIGH transceiver reset.
After the link sets this bit, the PHY will assert DIR and reset the digital core. This does not reset
the ULPI interface or the ULPI register set.
When reset is completed, the PHY will de-assert DIR and automatically clear this bit, followed
by an RXCMD update to the link.
0b — Do not reset (default)
1b — Reset
The link must wait for DIR to de-assert before using the ULPI bus. Does not reset the ULPI
interface or ULPI register set.
Operation Mode: Selects the required bit-encoding style during transmit.
00b — Normal operation (default)
01b — Non-driving
10b — Disable bit-stuffing and NRZI encoding
11b — Do not automatically add SYNC and EOP when transmitting; must be used only for
high-speed packets
Termination Select: Controls the internal 1.5 k full-speed pull-up resistor and 45
high-speed terminations. Control over bus resistors changes, depending on
XCVRSELECT[1:0], OPMODE[1:0], DP_PULLDOWN and DM_PULLDOWN, as shown in
Table
Transceiver Select: Selects the required transceiver speed.
00b — Enable the high-speed transceiver
01b — Enable the full-speed transceiver (default)
10b — Enable the low-speed transceiver
11b — Enable the full-speed transceiver for low-speed packets (full-speed preamble is
automatically prefixed)
IND_PASS
R/W/S/C
THRU
6
0
7.
R/W/S/C
COMPL
IND_
5
0
Rev. 01 — 30 May 2007
reserved
R/W/S/C
Table 26
4
0
provides the bit allocation of the register.
SUSPEND
CLOCK_
R/W/S/C
M
3
0
ISP1506A; ISP1506B
reserved
R/W/S/C
ULPI HS USB OTG transceiver
2
0
R/W/S/C
SERIAL
FSLS_
3PIN_
1
0
© NXP B.V. 2007. All rights reserved.
reserved
R/W/S/C
0
0
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