71M6541F-IGT/F Maxim Integrated Products, 71M6541F-IGT/F Datasheet - Page 45
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71M6541F-IGT/F
Manufacturer Part Number
71M6541F-IGT/F
Description
PMIC Solutions Precision Energy Meter IC
Manufacturer
Maxim Integrated Products
Type
Metering SoCr
Datasheet
1.71M6541F-DB.pdf
(165 pages)
Specifications of 71M6541F-IGT/F
Core
8051
Core Architecture
8051
Data Bus Width
8 bit
Data Ram Size
5 KB
Device Million Instructions Per Second
5 MIPS
Interface Type
I2C, ICE, SPI, UART
Maximum Clock Frequency
5 MHz
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Programmable I/os
30
Number Of Timers
2
On-chip Adc
22 bit
Operating Supply Voltage
3 V to 3.6 V
Package / Case
LQFP-64
Processor Series
8051
Program Memory Size
64 KB
Program Memory Type
Flash
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
71M6541F-IGT/F
Manufacturer:
MAXIM/TERIDIAN
Quantity:
411
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Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in
Each group of interrupt sources can be programmed individually to one of four priority levels (as shown in
Table 35)
(SFR 0xB9)
sequence as shown in
v1.1
Register
IP0
IP1
EX_WPULSE
EX_XPULSE
EX_YPULSE
EX_VPULSE
Changing interrupt priorities while interrupts are enabled can easily cause software defects. It is best
to set the interrupt priority registers only once during initialization before interrupts are enabled.
EX_EEX
EX_SPI
Name
Group
by setting or clearing one bit in the SFR interrupt priority register IP0 (SFR 0xA9) and one in IP1
Interrupt Enable
(Table
0
1
2
3
4
5
SFR 0xA9
SFR 0xB9
Address
36). If requests of the same priority level are received simultaneously, an internal polling
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel 0 interrupt
0x2701[7]
0x2700[7]
0x2700[6]
0x2700[5]
0x2701[6]
0x2701[5]
Location
Table 37
Table 36: Interrupt Priority Registers (IP0 and IP1)
© 2008–2011 Teridian Semiconductor Corporation
(MSB)
Bit 7
Table 34: Interrupt Priority Level Groups
–
–
IP1[x]
determines which request is serviced first.
–
0
0
1
1
Table 35: Interrupt Priority Levels
IE_WPULSE
IE_XPULSE
IE_VPULSE
IE_YPULSE
IE_EEX
IE_SPI
Name
Bit 6
–
–
Interrupt Flag
IP0[x]
0
1
0
1
IP0[5]
IP1[5]
Serial channel 1 interrupt
Bit 5
Group Members
SFR 0xE8[7]
SFR 0xE8[6]
SFR 0xE8[5]
SFR 0xF8[7]
SFR 0xF8[4]
SFR 0xF8[3]
Location
Level 0 (lowest)
Level 1
Level 2
Level 3 (highest)
Table
IP0[4]
IP1[4]
Bit 4
Priority Level
–
–
–
–
–
34.
SPI interrupt
EEPROM interrupt
CE_XPULSE interrupt (int 2)
CE_YPULSE interrupt (int 2)
CE_WPULSE interrupt (int 2)
CE_VPULSE interrupt (int 2)
IP0[3]
IP1[3]
Bit 3
Interrupt Description
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
IP0[2]
IP1[2]
Bit 2
–
IP0[1]
IP1[1]
Bit 1
IP0[0]
IP1[0]
(LSB)
Bit 0
45
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