71M6542F-IGT/F Maxim Integrated Products, 71M6542F-IGT/F Datasheet - Page 100

• Manufacturer Part Number: 71M6542F-IGT/F
• Description: PMIC Solutions Precision Energy Meter IC
• Manufacturer: Maxim Integrated Products
• Type: Metering SoCr

Specifications of 71M6542F-IGT/F

• Core: 8051
• Core Architecture: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 5 KB
• Device Million Instructions Per Second: 5 MIPS
• Interface Type: I2C, ICE, SPI, UART
• Maximum Clock Frequency: 5 MHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 51
• Number Of Timers: 2
• On-chip Adc: 22 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: LQFP-100
• Processor Series: 8051
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

•
In the demonstration code, temperature compensation behavior is determined by the values stored in the
PPMC and PPMC2 coefficients, which are setup by the MPU demo code at initialization time from values
that are previously stored in EEPROM.
To disable temperature compensation in the demonstration code, PPMC and PPMC2 are both set to zero
for each of the three GAIN_ADJn channels. To enable temperature compensation, the PPMC and PPMC2
coefficients are set with values that match the expected temperature variation of the corresponding
channel.
For VREF compensation, both the linear coefficient PPMC and the quadratic coefficient PPMC2, are
determined for the 71M654x as described in
information on determining the PPMC and PPMC2 coefficients for the 71M6x01 VREF, refer to the
71M6xxx Data Sheet.
The compensation for the external error sources is accomplished by summing the PPMC value
associated with VREF with the PPMC value associated with the external error source to obtain the final
PPMC value for the sensor channel. Similarly, the PPMC2 value associated with VREF is summed with
the PPMC2 value associated with the external error source.
To determine the contribution of the current shunt sensor to the PPMC and PPMC2 coefficients, the
designer must either know the temperature coefficients of the shunt from its data sheet or obtain it by
laboratory measurement. The designer must consider component variation across mass production to
ensure that the product will meet its accuracy requirement across production.
4.8
I
SEGDIO3, as shown in
Pull-up resistors of roughly 10 kΩ to V3P3D (to ensure operation in BRN mode) should be used for both
SDCK and SDATA signals. The DIO_EEX[1:0] (I/O RAM 0x2456[7:6]) field in I/O RAM must be set to 01
in order to convert the DIO pins SEGDIO2 and SEGDIO3 to I
100
2
C EEPROMs or other I
GAIN_ADJ2 provides compensation for the remotely connected IB shunt current sensor and compensates
for the 71M6x01 VREF. The designer may optionally add compensation for the shunt connected to the
71M6x01 into the PPMC and PPMC2 coefficients for this channel.
Connecting I
Gain Adjustment Output
GAIN_ADJ0
GAIN_ADJ1
GAIN_ADJ2
Figure
2
2
C compatible devices should be connected to the DIO pins SEGDIO2 and
C EEPROMs
© 2008–2011 Teridian Semiconductor Corporation
Table 73: GAIN_ADJn Compensation Channels
39.
SEGDIO3/SDATA
Figure 39: I
SEGDIO2/SDCK
71M654x
CE RAM Address
0x40
0x41
0x42
4.7.2 Temperature Coefficients for the
2
10 k Ω
C EEPROM Connection
10 k Ω
2
71M6541D/F
C pins SDCK and SDATA.
EEPROM
SDCK
SDATA
V3P3D
VA
IA
IB
71M6542F
71M654x. For
VA, VB
IA
IB
v1.1