71M6542F-IGT/F Maxim Integrated Products, 71M6542F-IGT/F Datasheet - Page 120

• Manufacturer Part Number: 71M6542F-IGT/F
• Description: PMIC Solutions Precision Energy Meter IC
• Manufacturer: Maxim Integrated Products
• Type: Metering SoCr

Specifications of 71M6542F-IGT/F

• Core: 8051
• Core Architecture: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 5 KB
• Device Million Instructions Per Second: 5 MIPS
• Interface Type: I2C, ICE, SPI, UART
• Maximum Clock Frequency: 5 MHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 51
• Number Of Timers: 2
• On-chip Adc: 22 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: LQFP-100
• Processor Series: 8051
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

120
Name
PLL_FAST
PLS_MAXWIDTH[7:0]
PLS_INTERVAL[7:0]
PLS_INV
PORT_E
PRE_E
PREBOOT
RCMD[4:0]
RESET
RFLY_DIS
SFR FC[4:0]
SFRB2[7]
210A[7:0]
210B[7:0]
Location
210C[0]
270C[5]
210C[3]
2200[4]
2704[5]
2200[3]
© 2008–2011 Teridian Semiconductor Corporation
Rst Wk Dir
FF FF R/W
0
0
0
0
0
–
0
0
0
0
0
0
0
0
–
0
0
0
R/W
R/W
R/W
R/W
R/W Enables the 8x pre-amplifier.
R/W
R/W
W
R
Description
Controls the speed of the PLL and MCK.
1 = 19.66 MHz (XTAL * 600)
0 = 6.29 MHz (XTAL * 192)
PLS_MAXWIDTH[7:0] determines the maximum width of the pulse (low-going
pulse if PLS_INV=0 or high-going pulse if PLS_INV=1). The maximum pulse
width is (2*PLS_MAXWIDTH[7:0] + 1)*T
units of CK_FIR clock cycles. If PLS_INTERVAL[7:0] = 0 or
PLS_MAXWIDTH[7:0] = 255, no pulse width checking is performed and the
output pulses have 50% duty cycle. See
PLS_INTERVAL[7:0] determines the interval time between pulses. The time
between output pulses is PLS_INTERVAL[7:0]*4 in units of CK_FIR clock
cycles. If PLS_INTERVAL[7:0] = 0, the FIFO is not used and pulses are output
as soon as the CE issues them. PLS_INTERVAL[7:0] is calculated as follows:
PLS_INTERVAL[7:0]
updates per Mux frame / 4 )
For example, since the 71M654x CE code is written to generate 6 pulses in one
integration interval, when the FIFO is enabled (i.e., PLS_INTERVAL[7:0] ≠ 0)
and that the frame duration is 1950 CK_FIR clock cycles, PLS_INTERVAL[7:0]
should be written with Floor(1950 / 6 / 4) = 81 so that the five pulses are
evenly spaced in time over the integration interval and the last pulse is issued
just prior to the end of the interval. See
Inverts the polarity of WPULSE and VARPULSE. Normally, these pulses are
active low. When inverted, they become active high. PLS_INV has no effect
on XPULSE or YPULSE.
Enables outputs from the pins SEGDIO0-SEGDIO15. PORT_E = 0 after reset
and power-up blocks the momentary output pulse that would occur on
SEGDIO0 to SEGDIO15.
Indicates that pre-boot sequence is active.
When the MPU writes a non-zero value to RCMD[4:0], the IC issues a
command to the appropriate remote sensor. When the command is complete,
the IC clears RCMD[4:0].
When set, writes a one to WF_RSTBIT and then causes a reset.
Controls how the IC drives the power pulse for the 71M6x01. When set, the
power pulse is driven high and low. When cleared, it is driven high followed
by an open circuit fly-back interval.
= Floor ( Mux frame duration in CK_FIR cycles / CE pulse
I
2.3.6.2 VPULSE and
. Where T
2.3.6.2 VPULSE and
I
is PLS_INTERVAL[7:0] in
WPULSE.
WPULSE.
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