A40MX04-PQ100M Actel, A40MX04-PQ100M Datasheet - Page 84
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A40MX04-PQ100M
Manufacturer Part Number
A40MX04-PQ100M
Description
83MHZ/139MHZ 0.45UM TECHNOLOGY 3.3V/5V
Manufacturer
Actel
Datasheet
1.A40MX04-PQ100M.pdf
(123 pages)
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TMS, I/O
The TMS pin controls the use of the IEEE 1149.1
Boundary Scan pins (TCK, TDI, TDO). In flexible mode
when the TMS pin is set LOW, the TCK, TDI and TDO pins
are boundary scan pins. Once the boundary scan pins are
in test mode, they will remain in that mode until the
internal boundary scan state machine reaches the "logic
reset" state. At this point, the boundary scan pins will be
released and will function as regular I/O pins. The "logic
reset" state is reached 5 TCK cycles after the TMS pin is
set HIGH. In dedicated test mode, TMS functions as
specified in the IEEE 1149.1 specifications. IEEE JTAG
specification recommends a 10kΩ pull-up resistor on the
pin. BST pins are only available in A42MX24 and
A42MX36 devices.
1 -7 8
40MX and 42MX FPGA Families
Test Mode Select
v6.0
V
Input supply voltage for 40MX devices
V
Supply voltage for array in 42MX devices
V
Supply voltage for I/Os in 42MX devices
WD, I/O
When a wide decode module is used in a 42MX device
this pin can be used as a dedicated output from the wide
decode module. This direct connection eliminates
additional interconnect delays associated with regular
logic modules. To implement the direct I/O connection,
connect an output buffer of any type to the output of
the wide decode macro and place this output on one of
the reserved WD pins.
CC
CCA
CCI
Supply Voltage
Supply Voltage
Supply Voltage
Wide Decode Output
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