PEB20591HV22XP Lantiq, PEB20591HV22XP Datasheet - Page 42

• Manufacturer Part Number: PEB20591HV22XP
• Manufacturer: Lantiq

Specifications of PEB20591HV22XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

PRELIMINARY
Data Sheet
3.5
The VIP provides IEEE 1149.1-compatible boundary scan support to allow cost-effective
board testing. It consists of:
• Complete boundary scan test
• Test access port (TAP) controller
• Five dedicated pins: TCK, TMS, TDI, TDO (according to JTAG) and an additional
• One 32-bit IDCODE register
• Specific functions for the analog line interface pins LIna, b and SXna, b
3.5.1
The TAP controller implements the state machine defined in the JTAG standard IEEE
1149.1. Transitions on the pin TMS cause the TAP controller to perform a state change.
The TAP controller supports 7 instructions:
• 5 standard instructions
• 2 additional user-specific instructions for transmitting continuous pulses at the line
Table 10
Code
0000
0001
0010
0011
1111
1000
1001
TAP Controller Instructions
EXTEST. EXTEST is used to verify the board interconnections.
When the TAP controller is in the state “update DR”, all output pins are updated with the
falling edge of TCK. When it has entered state “capture DR” the levels of all input pins
are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically
done using the instruction SAMPLE/PRELOAD.
TRST pin to enable asynchronous resets to the TAP controller
interfaces LIna/b (60 kHz) and SXna/b (120 kHz)
JTAG Boundary Scan Test Interface
TAP Controller
Instruction
EXTEST
INTEST
SAMPLE/PRELOAD
IDCODE
BYPASS
User specific
User specific
TAP Controller Instruction Codes Overview
Function
External testing
Internal testing
Snap-shot testing
Reading ID code register
Bypass operation
Continuous pulses on LIna and LInb
Continuous pulses on SXna and SXnb
34
Interface Description
PEB 20590
PEB 20591
2001-03-01