MC145572PBR2 Freescale Semiconductor, MC145572PBR2 Datasheet - Page 122
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MC145572PBR2
Manufacturer Part Number
MC145572PBR2
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC145572PBR2.pdf
(264 pages)
Specifications of MC145572PBR2
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Not Compliant
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7–6
Tx DATA
NOTE: Due to internal delays, the actual sync word marker on the TxP and TxN pins occurs 8 quats later than the TxSFS pulse.
LT
- IRQ1, IRQ2
- BR1 UPDATED FROM
- R6 UPDATED FROM
Rx DATA
See Figure 10–20.
RECEIVED M4 CHANNEL
RECEIVED eoc CHANNEL
- TRANSMITTED M4 UPDATED
- TRANSMITTED M5 AND M6 CHANNELS
- TRANSMITTED eoc UPDATED FROM R6
- TxSFS PULSE OUTPUT ON PIN 25
FROM BR0
UPDATED FROM BR2
(SEE NOTE)
8
LT
QUAT 120
8
1
QUAT 117
Freescale Semiconductor, Inc.
1
For More Information On This Product,
Figure 7–3. LT Mode Maintenance Channel Updates
60, + 8, - 2 QUATS
2
Go to: www.freescale.com
2
3
MC145572
3
1 SUPERFRAME (12 ms)
- IRQ0, IRQ2
- BR3 UPDATED FROM
-
- R6 UPDATED FROM
4
RECEIVED M5 AND M6
CHANNELS
febe
RECEIVED eoc CHANNEL
- TRANSMITTED eoc UPDATED FROM R6
1 SUPERFRAME (12 ms)
4
STATUS BIT UPDATED
QUAT 120
5
QUAT 117
5
6
6
7
- IRQ1, IRQ2
- BR1 UPDATED FROM
-
- R6 UPDATED FROM
7
RECEIVED M4 CHANNEL
nebe
RECEIVED eoc CHANNEL
8
STATUS BIT UPDATED
QUAT 120
8
MOTOROLA
1
1
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