MC145572PBR2 Freescale Semiconductor, MC145572PBR2 Datasheet - Page 58
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MC145572PBR2
Manufacturer Part Number
MC145572PBR2
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC145572PBR2.pdf
(264 pages)
Specifications of MC145572PBR2
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Not Compliant
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4–22
eoc Trinal–Check Mode (b7, b6 = 1,0)
The eoc Trinal–Check operation checks for three identical consecutive eoc messages being received
before loading the eoc message into R6. Register R6 is always updated with the received message
when the third identical consecutive message is received.
In Trinal–Check mode when operating as an LT, the trinal–check is automatically restarted whenever
a new message is written to the Superframe Framer’s R6 register for transmission. The eoc Trinal–
Check is reset whenever the Linkup (NR1(b3)) or Superframe Sync (NR1(b1)) bits are 0.
When operating as an NT in Trinal–Check mode, received eoc messages are automatically transmitted
back by the Superframe Framer if the address is either the NT1 or broadcast address. This continues
until three valid consecutive identical messages have been received. If the eoc address in the received
eoc message is not 0 or 7, the Hold message is substituted and automatically transmitted back to
the LT. Once three valid consecutive identical messages have been received, the deframer updates
Register R6. Once R6 has been updated with the received message, the Superframe Framer’s Regis-
ter R6 (written to by a SCP interface operation) is transmitted. It is up to the microcontroller firmware
to handle the eoc message and place a response into R6 before the U–chip sends the next eoc frame
out to the LT (see Figure 4–2). Register R6 will be repeated throughout all subsequent eoc frames
until it is altered by another CPI interface write to it, or the received eoc message changes.
Automatic eoc Processor Mode (b7 = 0, b6 = Don’t Care)
An Automatic eoc Processor is provided in the NT mode. This processor operates the eoc in accor-
dance with ANSI T1.601–1992. The processor recognizes eoc messages addressed to either the NT1
or the broadcast address. The processor decodes the messages in Table 4–10 and then takes the
action indicated. If a properly addressed message is received that is not listed in the table, the “Unable
to Comply” message is transmitted in response. If an improperly addressed message is received,
the “Hold State” message is transmitted with the NT1 address. Whenever operating in this mode,
the eoc Trinal–Check operation continues to function and R6 will be loaded with the eoc message
that the Automatic eoc Processor decodes. Note that because the Automatic eoc Processor is an
NT mode only function, selecting mode 0,0 in the LT mode is equivalent to mode 1,0.
Regardless of eoc mode, Register R6 will not be altered while Superframe Detect (BR3(b0)) is a 0.
When the automatic eoc mode is enabled, bits in BR6 are not set when loopback messages are re-
ceived.
M4 Control 1:0
These bits control the M4 handling capability of the U–interface transceiver. The default mode setting
is b5, b4 = 0,0. In all of the modes, BR1 will not be loaded and an IRQ1 (NR3(b1)) will not be issued
unless both Linkup (NR1(b3)) and Superframe Sync (NR1(b1)) are 1s. When OR7(b0) is set to 1;
uoa, act, sai, and dea bits in the M4 channel are trinal–checked. See Table 4–11.
Operate 2B + D Loopback
Operate B1 Channel Loopback
Operate B2 Channel Loopback
Request Corrupted crc
Notify of Corrupted crc
Return to Normal
Hold State
eoc Message
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 4–10. Automatic eoc Processor Functions
Go to: www.freescale.com
Invokes a loopback to the U–interface at the IDL interface of the B1, B2, and D chan-
nels. Transparency will be determined by the setting of BR6(b4), U–loop transparent.
Invokes a loopback to the U–interface at the IDL interface of the B1 channel. The
loopback is transparent.
Invokes a loopback to the U–interface at the IDL interface of the B2 channel. The
loopback is transparent.
Equivalent to setting BR8(b3) to a 1.
None.
Resets all of the previously invoked eoc functions.
Maintains previously invoked eoc functions.
MC145572
Automatic eoc Processor Response
MOTOROLA
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