T7295-6EL LSI, T7295-6EL Datasheet - Page 51

• Manufacturer Part Number: T7295-6EL
• Manufacturer: LSI

Specifications of T7295-6EL

• Lead Free Status / Rohs Status: Not Compliant

Data Sheet
April 1997
Lucent Technologies Inc.
Timing Characteristics
Multiplexed Address and Data
Both address and data on AD7—AD0.
Table 26. Multiplexed Address and Data
* This is the time needed to update the receive FIFO status RQS (R4—B[6—0]).
† See Figure 24 for data clock period specification.
Symbol on
Diagram
M
C
D
G
H
N
O
A
B
E
F
K
P
J
L
I
tWRHWRL
tWRLWRH
tWRHCSH
tRDHCSH
tMCLMCL
tCSLRWL
tRDLRDH
tRDHRDL
tADHALL
tALLRWL
tALHALL
tADVALL
tDVWRH
tWRHDI
tRDLDV
tRDHDI
Name
ALE Pulse Width
Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to
CS
Data Valid to
Data Hold After
WR
RD
RD
RD
RD
WR
RD
WR
between writes)
RD
between reads); Read R3 to Read R4*
Master Clock Period
(continued)
Low to
Pulse Width
Low to Data Valid (R2 or R4)
Low to Data Valid (all others)
High to Data 3-state
High to
High to
Pulse Width
High to
High to
RD
CS
RD
WR
CS
RD
WR
or
High
Parameter
Low (minimum time
High
or
Low (minimum time
WR
WR
High
WR
High
†
Low
Low
T7121 HDLC Interface for ISDN (HIFI-64)
tMCLMCL + 40
2 tMCLMCL
4 tMCLMCL
83.3
Min
25
25
35
35
10
40
10
—
—
0
0
0
tMCLMCL + 40
3 tMCLMCL
<tDCLDCL
tMCLMCL
Max
25
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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