T7295-6EL LSI, T7295-6EL Datasheet - Page 58

• Manufacturer Part Number: T7295-6EL
• Manufacturer: LSI

Specifications of T7295-6EL

• Lead Free Status / Rohs Status: Not Compliant

T7121 HDLC Interface for ISDN (HIFI-64)
Timing Characteristics
Table 29. Concentration Highway Timing for CMS = 1
1. Edge of clock used to sample FS (selected by the FE bit [R0—B6]).
2. Edge of first bit transmission (see Figures 12—20).
3. The CLKXI bit (R9—B4) controls the edge on which data is transmitted, and the CLKRI bit (R9—B0) controls the edge on which received
58
Symbol on
data is sampled.
Diagram
C
D
G
H
A
B
E
F
J
I
(CLKRI = 0)
(CLKXI = 1)
(CMS = 1, CLKXI = 1, CLKRI = 0, FSPOL = 1, RMB = TBM = 11111111)
AND/OR
(FE = 0)
TSCA
CLKX
CLKR
DRA
DRB
DXA
DXB
OR
FS
tFSHCKE
tDCLDCL
tCKEFSL
tDVRCE
tCETSL
tCETST
tRCEDI
tCEDT
tCEDV
tFSFS
Name
3
3
CLKX/R Period
FS High to CLKX/R Edge Selected
FS Hold After CLKX/R Edge Selected
CLKX Edge to Data Valid
CLKX Edge to Data 3-state
CLKX Edge to
CLKX Edge to
Receive Data Setup Time
Receive Data Hold Time
FS Period
(continued)
Figure 25. Timing for Concentration Highway
B
C
1
D
F
Parameter
TSCA
TSCA
A
2
BIT 0
Low
3-state
H
I
D
J
18 tDCLDCL 1024 tDCLDCL
BIT 7
Min
122
50
50
25
20
—
—
0
0
E
G
tDCLDCL – 30
Lucent Technologies Inc.
Max
80
45
70
70
—
—
—
—
Data Sheet
April 1997
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5-5051