MT29C4G96MAZAPCJA-5 IT Micron Technology Inc, MT29C4G96MAZAPCJA-5 IT Datasheet - Page 7

• Manufacturer Part Number: MT29C4G96MAZAPCJA-5 IT
• Description: MICMT29C4G96MAZAPCJA-5_IT 4G+4G MCP 137B
• Manufacturer: Micron Technology Inc

Table 2:
PDF: 09005aef8326e5ac / Source: 09005aef8326e59a
152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
CE1#, CE0#
I/O[15:0]
Symbol
I/O[7:0]
LOCK
(x16)
WE#
WP#
R/B#
ALE
CLE
RE#
(x8)
V
CC
x8/x16 NAND Ball Descriptions
Output
output
Supply
Input/
Input
Input
Input
Input
Input
Input
Input
Type
Notes: 1. Balls marked RFU may or may not be connected internally. These balls should not be used.
Address latch enable: When ALE is HIGH, addresses can be transferred to the on-chip address
register.
Chip enable: Gates transfers between the host system and the NAND Flash device.
Command latch enable: When CLE is HIGH, commands can be transferred to the on-chip
command register.
When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled. To disable BLOCK
LOCK, connect LOCK to V
Read enable: Gates information from the NAND device to the host system.
Write enable: Gates information from the host system to the NAND device.
Write protect: Driving WP# LOW blocks ERASE and PROGRAM operations.
Data inputs/outputs: The bidirectional I/Os transfer address, data, and instruction information.
Data is output only during READ operations; at other times the I/Os are inputs.
I/O[15:8] are RFU
Ready/busy: Open-drain, active-LOW output that indicates when an internal operation is in
progress.
V
CC
: NAND power supply.
Contact the factory for details.
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
1
for NAND x8 devices.
SS
during power-up, or leave it unconnected (internal pull-down).
7
Description
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
©2008 Micron Technology, Inc. All rights reserved.
Preliminary