MT29C4G96MAZAPCJA-5 IT Micron Technology Inc, MT29C4G96MAZAPCJA-5 IT Datasheet - Page 8

• Manufacturer Part Number: MT29C4G96MAZAPCJA-5 IT
• Description: MICMT29C4G96MAZAPCJA-5_IT 4G+4G MCP 137B
• Manufacturer: Micron Technology Inc

Table 3:
Table 4:
PDF: 09005aef8326e5ac / Source: 09005aef8326e59a
152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
Symbol
V
NC
RFU
LDQS, UDQS
CKE0, CKE1
LDM, UDM
CS1#, CS0#
SS
BA1, BA0
DQ[15:0]
DQ[31:0]
DQS[3:0]
Symbol
CK, CK#
DM[3:0]
A[14:0]
CAS#
RAS#
V
(x16)
(x32)
(x16)
(x32)
(x16)
(x32)
1
WE#
V
V
TQ
DDQ
SSQ
DD
x16/x32 LPDDR Ball Descriptions
Non-Device-Specific Ball Descriptions
Output
output
output
Supply
Supply
Supply
Supply
Input/
Input/
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
Type
–
–
Notes: 1. Balls marked RFU may or may not be connected internally. These balls should not be used.
Address inputs: Specifies the row or column address. Also used to load the mode registers. The
maximum LPDDR address is determined by density and configuration. Consult the LPDDR
product data sheet for the maximum address for a given density and configuration. Unused
address pins become RFU.
Bank address inputs: Specifies one of the 4 banks.
Column select: Specifies the command to execute.
CK is the system clock. CK and CK# are differential clock inputs. All address and control signals
are sampled and referenced on the crossing of the rising edge of CK with the falling edge of
CK#.
Clock enable:
CKE0 is used for a single LPDDR product.
CKE1 is used for dual LPDDR products.
Chip select:
CS0# is used for a single LPDDR product.
CS1# is used for dual LPDDR products and is considered RFU for single LPDDR MCPs.
Data mask: Determines which bytes are written during WRITE operations.
For x16 LPDDR, unused DM balls become RFU.
Row select: Specifies the command to execute.
Write enable: Specifies the command to execute.
Data bus: Data inputs/outputs.
DQ[31:16] are RFU for x16 LPDDR devices.
Data strobe: Coordinates READ/WRITE transfers of data; one DQS per DQ byte.
For x16 LPDDR, unused DQS balls become RFU.
Temperature sensor output: TQ HIGH when LPDDR T
V
V
V
V
No connect: Not internally connected.
Reserved for future use.
DD
DDQ
SSQ
SS
: Shared ground.
: LPDDR power supply.
: LPDDR I/O ground.
: LPDDR I/O power supply.
Contact the factory for details.
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
8
Description
Description
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
J
exceeds 85°C.
©2008 Micron Technology, Inc. All rights reserved.
Preliminary