CorePCI Eval Board MICROSEMI, CorePCI Eval Board Datasheet - Page 31

• Manufacturer Part Number: CorePCI Eval Board
• Description: MCU, MPU & DSP Development Tools CorePCI v5.41
• Manufacturer: MICROSEMI

Specifications of CorePCI Eval Board

• Processor To Be Evaluated: SX-A device
• Interface Type: RS-232

Notes:
1. In the example, the PCI Master interrupts the flow of data by de-asserting the IRDYn sign in cycle 4. One cycle later, RD_BE_NOW
2. The backend can also interrupt the flow of data by de-asserting the RD_BE_RDY signal. The backend should be prepared to provide
Figure 14 • PCI Read Illustrating both IRDYn and TRDYn De-Assertion
Backend Latency Control
Some backends require the address to be available at
least one cycle prior to data being valid. This is true for
most synchronous backends. In order to support this
need, CorePCI provides the PIPE_FULL_CNT control bus to
the backend. This bus can be used to define the relative
delay
PIPE_FULL_CNT is set to '000', the address will be
expected to be coincident with the data and the data
should be valid whenever the *NOW lines are asserted.
When PIPE_FULL_CNT is set to a non-zero value, then the
operation of the backend is as follows:
MEM_ADDRESS[23:2]
signal becomes inactive indicating that the backend should stop supplying data.
one additional DWORD of data to the PCI bus prior to halting the data flow. One cycle after RD_BE_RDY is de-asserted, the
RD_BE_NOW signal is driven inactive, which is then followed by the de-assertion of TRDYn.
MEM_DATA[31:0]
between
RD_BE_NOW
RD_BE_RDY
DP_START
DP_DONE
DEVSELn
FRAMEn
CBE[3:0]
AD[31:0]
STOPn
TRDYn
IRDYn
PAR
CLK
address
data2
data3
add3
Pd1
1
and
data3
data4
add4
Pd2
2
data4
data5
data.
add5
Pd3
3
data6
add6
Pd4
When
4
data5
5
the
add7
Pd5
6
v4.0
data6
data7
Figure 15
with the PIPE_FULL_CNT set to '001'.
7
• The backend asserts the *RDY signal.
• The *NOW signal will assert, and the address will
• Once the initial time-out occurs, valid data must
data7
data8
add8
Pd6
byte enables
begin incrementing. However, the data is not
expected to be valid until N cycles after the value
defined on the PIPE_FULL_CNT bus.
be available whenever the *NOW signal is
asserted.
8
is an example of this function for a read cycle
data8
data9
add9
Pd7
9
data9
Pd8
10
Pd9
11
add10
12
data10
13
data10
data11
add11
14
CorePCI v5.41
data11
data12
add12
Pd10
15
data12
data13
add13
Pd11
16
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