CorePCI Eval Board MICROSEMI, CorePCI Eval Board Datasheet - Page 6

• Manufacturer Part Number: CorePCI Eval Board
• Description: MCU, MPU & DSP Development Tools CorePCI v5.41
• Manufacturer: MICROSEMI

Specifications of CorePCI Eval Board

• Processor To Be Evaluated: SX-A device
• Interface Type: RS-232

CorePCI IP Functional Block
Diagram
CorePCI consists of six major functional blocks, shown in
Figure 2 on page
machine,
dataphase state machine, the datapath, parity, and the
configuration block. All of the blocks shown are required
to implement the Target+DMA and Target+Master
functions. For the Target-only core, the DMA state
machine is eliminated. For the Master-only core, the
configuration block is not required.
The DMA, address phase, and dataphase state machines
control the core’s outputs and also the dataflow
between the PCI bus and the backend. The remaining
modules define the datapath logic for CorePCI.
DMA State Machine
The DMA state machine is responsible for obtaining
Master ownership of the PCI bus and launching a data
transfer by asserting FRAMEn. Once a burst transaction
has begun, the DMA state machine tracks the transfer
count and terminates the burst by de-asserting the
FRAMEn signal and releasing Master ownership of the
PCI bus. In addition to basic Master control, the DMA
module also implements the DMA support registers, PCI
Start Address, RAM Start Address, and DMA Control.
Address Phase State Machine
The address phase state machine is responsible for
monitoring the PCI bus and determining if a PCI
transaction is targeting CorePCI. When a hit is detected,
the DP_START/DP_START64 signals are activated, setting
off the dataphase machine and backend logic. The
address phase state machine also determines the cycle
type and provides this information on the RD_CYC,
WR_CYC, BAR0_MEM_CYC, BAR1_CYC, and CONFIG_CYC
outputs.
Dataphase State Machine
The
controlling the PCI output signals and coordinating the
data transfers with the backend logic. When operating
as a Target, the PCI outputs are TRDYn, DEVSELn, and
STOPn. When operating as a Master, IRDYn is the
primary PCI output. Data transfers to the backend are
coordinated using the signals RD_BE_RDY, RD_BE_NOW,
WR_BE_RDY, and WR_BE_NOW. The two "BE_RDY"
inputs indicate that the backend is ready to transmit or
receive data. The "BE_NOW" signals are synchronous
data strobes and indicate that a data transfer will occur
on the next rising edge of the clock. The dataphase state
machine also drives the DP_DONE output active at the
end of the PCI transfer.
6
CorePCI v5.41
dataphase
the
address
state
7. These blocks are the DMA state
machine
phase
state
is
responsible
machine,
the
for
v4.0
Datapath
The datapath module provides the steering and registers
for the data between the PCI bus and the backend.
Additionally, the datapath contains the address counters
and increments the value after each data transaction.
Parity
The parity block generates and checks parity on the PCI
bus.
Configuration
The configuration block contains the configuration
register file for the Target controller. These registers
include the ID, status, control, and the base address
registers. The core implements a single function Type 0
configuration space.
Data Transactions
CorePCI is designed to be fully compliant for all transfer
types,
transactions. Burst transfers can operate with either
zero, one, or more wait states. Normally, CorePCI will
burst data with zero wait states; however, for slow
response peripherals, CorePCI can insert wait states
under the control of the backend. During Target
operation, wait states are inserted by driving TRDYn
high. During Master operation, CorePCI drives IRDYn
high to insert wait states.
I/O Signal Descriptions
The PCI and backend signals for CorePCI are defined in
Table 5 on page 8
purposes of this data sheet, the following signal type
definitions are used:
• Input: Standard input-only signal.
• Output:
• Tristate Output: Standard active driver that can be
• Bidirectional (referred to as t/s in the PCI
• Sustained Tristate (s/t/s in the PCI specification): A
• Open Drain: Drive to '0' only output. A pull-up is
continuously.
tristated.
specification): A combination input and t/s output
pin.
term used to describe either bidirectional or t/s
output pins. The STS term indicates that the signal
should always be driven to a logic '1' before the
pin is tristated.
required to sustain the high-impedance state to a
logic '1' and is provided by the PCI backplane.
including
Standard
both
and
Table 6 on page
single
active
DWORD
driver
that
9. For the
and
drives
burst