CorePCI Eval Board MICROSEMI, CorePCI Eval Board Datasheet - Page 34

• Manufacturer Part Number: CorePCI Eval Board
• Description: MCU, MPU & DSP Development Tools CorePCI v5.41
• Manufacturer: MICROSEMI

Specifications of CorePCI Eval Board

• Processor To Be Evaluated: SX-A device
• Interface Type: RS-232

Notes:
1. During a normal PCI transaction, the backend reaches a point where it is unable to deliver data and de-asserts RD_BE_RDY.
2. If the backend cannot deliver new data within 8 cycles, then it should assert the BUSY signal.
3. The Target initiates a disconnect by asserting the STOPn signal.
4. The Master will begin cycle termination by de-asserting FRAMEn first, and then IRDYn on a subsequent cycle.
Figure 18 • Target Disconnect Without Data
Backend Arbitration
When the backend needs to take control of the backend
bus, it should arbitrate for control using the BE_REQ and
BE_GNT handshake signals
Notes:
1. Arbitration begins by the backend asserting the BE_REQ signal. The Target Controller will grant control as soon as the PCI controller
2. The backend will maintain control as long as the BE_REQ signal remains active.
3. To relinquish control, the backend will de-assert the BE_REQ and BE_GNT will de-assert on the following cycle.
Figure 19 • Backend Arbitration Cycle
3 4
CorePCI v5.41
goes into an IDLE state.
MEM_ADDRESS[23:2]
MEM_DATA[31:0]
RD_BE_NOW
RD_BE_RDY
DP_START
DP_DONE
AD[31:0]
DEVSELn
FRAMEn
CBE[3:0]
(Figure 19 on page
TRDYn
STOPn
IRDYn
BUSY
BE_GNT
BE_REQ
PAR
CLK
CLK
data4 data5 data6 data7
data5 data6 data7
add5
Pd3
1
add6
Pd4
2
34).
add7
Pd5
3
data8
add8
Pd6
4
v4.0
data8
Pd7
5
Interrupt
To initiate an interrupt, the backend needs to assert the
EXT_INTn input
the PCI INTAn interrupt signal will assert.
Pd8
6
7
8
(Figure 20 on page
add9
9
10
11
35). Two cycles later
12