PIC18F45J10-I/PT Microchip Technology Inc., PIC18F45J10-I/PT Datasheet - Page 84

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PIC18F45J10-I/PT

Manufacturer Part Number
PIC18F45J10-I/PT
Description
44 PIN, 32 KB FLASH, 1024 RAM
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F45J10-I/PT

A/d Inputs
13-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
0 Bytes
Input Output
32
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin TQFP
Programmable Memory
32K Bytes
Ram Size
1K Bytes
Speed
40 MHz
Timers
1-8 bit, 2-16 bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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PIC18F45J10 FAMILY
REGISTER 8-2:
DS39682B-page 82
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RBPU: PORTB Pull-up Enable bit
1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
INTEDG2: External Interrupt 2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
Unimplemented: Read as ‘0’
TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
Unimplemented: Read as ‘0’
RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
bit 7
INTCON2: INTERRUPT CONTROL REGISTER 2
Legend:
R = Readable bit
-n = Value at POR
Note:
R/W-1
RBPU
Interrupt flag bits are set when an interrupt condition occurs regardless of the state
of its corresponding enable bit or the global interrupt enable bit. User software should
ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This
feature allows for software polling.
INTEDG0
R/W-1
INTEDG1
R/W-1
Preliminary
W = Writable bit
‘1’ = Bit is set
INTEDG2
R/W-1
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
TMR0IP
R/W-1
© 2006 Microchip Technology Inc.
x = Bit is unknown
U-0
R/W-1
RBIP
bit 0

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