K4S641632D-LL60 Samsung Semiconductor, K4S641632D-LL60 Datasheet
K4S641632D-LL60
Specifications of K4S641632D-LL60
Related parts for K4S641632D-LL60
K4S641632D-LL60 Summary of contents
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... K4S641632D * Samsung Electronics reserves the right to change products or specification without notice. 64Mbit SDRAM 1M x 16Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.3 June 2000 CMOS SDRAM Rev. 0.3 June 2000 ...
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... K4S641632D Revision History Revision 0.1 (May 2000) • Changed tOH of K4S280432C-TC75/TL75 from 2.7ns to 3.0ns. Revision 0.2 (May 2000) • Added -70 (7.0ns) Speed. Revision 0.3 (June 2000) • Added -60 (6.0ns) and -55(5.5ns) Speed. CMOS SDRAM Rev. 0.3 June 2000 ...
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... CKE Samsung Electronics reserves the right to change products or specification without notice. * GENERAL DESCRIPTION The K4S641632D is 67,108,864 bits synchronous high data rate Dynamic RAM organized 1,048,576 words by 16 bits, fabricated with SAMSUNG s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle ...
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... K4S641632D PIN CONFIGURATION (Top view) PIN FUNCTION DESCRIPTION Pin Name CLK System clock CS Chip select CKE Clock enable Address Bank select address 0 1 RAS Row address strobe CAS Column address strobe WE Write enable L(U)DQM Data input/output mask DQ ~ Data input/output Power supply/ground ...
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... AC. The overshoot voltage duration (min) = -2.0V AC. The undershoot voltage duration Any input DDQ Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. The VDD condition of K4S641632D-55/60 is 3.135V~3.6V. CAPACITANCE (V = 3.3V Pin Clock RAS, CAS, WE, CS, CKE, DQM Address ...
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... I NS CC3 Operating current I CC4 (Burst mode) Refresh current I CC5 Self refresh current I CC6 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S641632D-TC** 4. K4S641632D-TL** 5. Unless otherwise noted, input swing IeveI is CMOS Test Condition Burst length = (min CKE V (max 10ns ...
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... Output timing measurement reference level Output load condition Output 870 (Fig output load circuit Notes : 1. The DC/AC Test Output Load of K4S641632D-55/60 is 30pF. 2. The VDD condition of K4S641632D-55/60 is 3.135V~3.6V. OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay ...
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... K4S641632D AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter Symbol CAS latency=3 CLK cycle t CC time CAS latency=2 CAS latency=3 CLK to valid t SAC output delay CAS latency=2 CAS latency=3 Output data t OH hold time CAS latency=2 CLK high pulse width t CH CLK low pulse width ...
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... K4S641632D IBIS SPECIFICATION I Characteristics (Pull-up) OH 100MHz 100MHz Voltage 133MHz 133MHz Min Max (V) I (mA) I (mA) 3.45 -2.4 3.3 -27.3 3.0 0.0 -74.1 2.6 -21.1 -129.2 2.4 -34.1 -153.3 2.0 -58.7 -197.0 1.8 -67.3 -226.2 1.65 -73.0 -248.0 1.5 -77.9 -269.7 1.4 -80.8 -284 ...
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... K4S641632D V Clamp @ CLK, CKE, CS, DQM & (V) I (mA) DD 0.0 0.0 0.2 0.0 0.4 0.0 0.6 0.0 0.7 0.0 0.8 0.0 0.9 0.0 1.0 0.23 1.2 1.34 1.4 3.02 1.6 5.06 1.8 7.35 2.0 9.83 2.2 12.48 2.4 15.30 2.6 18.31 V Clamp @ CLK, CKE, CS, DQM & DQ ...
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... K4S641632D SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Entry Refresh Self refresh Exit Bank active & row addr. Read & Auto precharge disable column address Auto precharge enable Write & Auto precharge disable column address Auto precharge enable ...