K4S641632D-LL60 Samsung Semiconductor, K4S641632D-LL60 Datasheet - Page 3

• Manufacturer Part Number: K4S641632D-LL60
• Manufacturer: Samsung Semiconductor
• Type: SDRAMr

Specifications of K4S641632D-LL60

• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 160mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

1M x 16Bit x 4 Banks Synchronous DRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
FUNCTIONAL BLOCK DIAGRAM
K4S641632D
clock
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
ADD
CLK
LCKE
*
CLK
Samsung Electronics reserves the right to change products or specification without notice.
LRAS
CKE
Bank Select
LCBR
CS
LWE
RAS
Timing Register
LCAS
CAS
Latency & Burst Length
GENERAL DESCRIPTION
rate Dynamic RAM organized as 4 x 1,048,576 words by 16
bits, fabricated with SAMSUNG s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programma-
ble burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
ORDERING INFORMATION
Programming Register
WE
Data Input Register
K4S641632D-TC/L55
K4S641632D-TC/L60
K4S641632D-TC/L70
K4S641632D-TC/L75
K4S641632D-TC/L80
K4S641632D-TC/L1H
K4S641632D-TC/L1L
The K4S641632D is 67,108,864 bits synchronous high data
Column Decoder
1M x 16
1M x 16
1M x 16
1M x 16
L(U)DQM
Part No.
LWCBR
183MHz(CL=3)
166MHz(CL=3)
143MHz(CL=3)
133MHz(CL=3)
125MHz(CL=3)
100MHz(CL=2)
100MHz(CL=3)
Max Freq.
Rev. 0.3 June 2000
CMOS SDRAM
LDQM
Interface Package
LVTTL
LWE
LDQM
DQi
TSOP(II)
54